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authorMartin Roth <martinroth@google.com>2018-01-10 16:56:04 -0800
committerMartin Roth <martinroth@google.com>2018-01-12 00:57:00 +0000
commit3441292ecda5e76a98ff63f55fc45d010fc76188 (patch)
tree2ecf436040cbd04d7c06243dbdf7455376843e84
parent6719862de80cec31a910ab1cc39fb7d3ba7b9a80 (diff)
mainboard/google/kahlee: Enable PCIe Lane 2
The Port initializer had been changed from PortDisabled to PortEnabled, but engine inializer hadn't been updated from PcieUnusedEngine to PciePortEngine. Update this so the port works. Also change disabled port to PcieUnusedEngine. BUG=b:71818026 TEST=PCIe device now shows up on D2F4 Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23210 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 622152b8e6..aa0edf7d91 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -52,7 +52,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2(
PortDisabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */
@@ -68,7 +68,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2(
PortEnabled, /* mPortPresent */
ChannelTypeExt6db, /* mChannelType */