diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-23 10:19:28 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 11:09:05 +0000 |
| commit | 3215e004e4dae1c3aa7ce55da9f37ac9256a6835 (patch) | |
| tree | 9131b777580ddeaba1dcc7ebb92b9cbccc41ef7a | |
| parent | 68aca73cfd3602e2c40ab851d3e0e1c016de3b23 (diff) | |
soc/amd/common/acpi/gpio_bank_lib: drop unused methods
Those methods were only in the non-common Stoneyridge GPIO ACPI code
that got dropped, so drop those unused methods too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/common/acpi/gpio_bank_lib.asl | 84 |
1 files changed, 0 insertions, 84 deletions
diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 579ff6888a..eba263e58a 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -36,90 +36,6 @@ Method (GPWR, 0x2, Serialized) TEMP = Arg1 } -Method (GPGB, 0x2) -{ - /* - * Returns the desired byte - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - */ - Local2 = Arg1 * 8 - Return ((GPRD (Arg0) >> Local2) & 0x000000FF) -} - -Method (GPSB, 0x3) -{ - /* - * Reads dword, replace byte, write back dword - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - * Arg2 - Value - */ - Local2 = Arg1 * 8 - Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 - Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 - GPWR (Arg0, Local4) -} - -/* Read pin control byte 0 */ -Method (GPR0, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 0)) -} - -/* Read pin control byte 1 */ -Method (GPR1, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 1)) -} - -/* Read pin control byte 2 */ -Method (GPR2, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 2)) -} - -/* Read pin control byte 3 */ -Method (GPR3, 0x1) -{ - Return (GPGB(Arg0, 3)) -} - -/* Write pin control byte 0 */ -Method (GPW0, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 0, Arg1) -} - -/* Write pin control byte 1 */ -Method (GPW1, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 1, Arg1) -} - -/* Write pin control byte 2 */ -Method (GPW2, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 2, Arg1) -} - -/* Write pin control byte 3 */ -Method (GPW3, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 3, Arg1) -} - /* * Set GPIO Output Value * Arg0 - GPIO Number |