diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-13 14:05:09 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-16 15:56:50 +0200 |
| commit | 3038b48de36d69c26c29977d1ff8afc7953febf3 (patch) | |
| tree | 20c377033c65b2c5c6a0fcd9524ab37248844c28 | |
| parent | 95d6dd21c95ca1729024b79357b583aebd28f9cc (diff) | |
soc/intel/apollolake: Removing some menuconfig options
Does not need to changeable in menuconfig.
Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b80941d0dd..deb510eda3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -113,11 +113,11 @@ config PCR_BASE_ADDRESS This option allows you to select MMIO Base Address of sideband bus. config DCACHE_RAM_BASE - hex "Base address of cache-as-RAM" + hex default 0xfef00000 config DCACHE_RAM_SIZE - hex "Length in bytes of cache-as-RAM" + hex default 0xc0000 help The size of the cache-as-ram region required during bootblock @@ -140,7 +140,7 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL - hex "MMIO base address for UART" + hex default 0xde000000 config SOC_UART_DEBUG |