diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-03-14 21:43:04 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-03-16 04:43:11 +0000 |
| commit | 2cfc862a3e4769ea94c23a109f1ca82dfbc47f1b (patch) | |
| tree | cc1242708b364e86b52cfd1a2b88dd548159d019 | |
| parent | 6d5e10c05d99c475e63bbe95012066f9c585cfb3 (diff) | |
soc/intel/apollolake: Add config option for enabling hotplug
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 60067735ce..af145c0259 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -534,6 +534,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, sizeof(silconfig->PcieRpClkReqNumber)); + memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, + sizeof(silconfig->PcieRpHotPlug)); + if (cfg->emmc_tx_cmd_cntl != 0) silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; if (cfg->emmc_tx_data_cntl1 != 0) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 7a1d16a1ad..fe845ab06c 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -46,6 +46,9 @@ struct soc_intel_apollolake_config { */ uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; + /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */ + uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ |