diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-10-08 09:08:55 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-28 21:32:06 +0000 |
| commit | 2cbe43890bfda129a5a8a72be634f5568d892d07 (patch) | |
| tree | 47d94eba857c097d923fadcf2bbc76c4713b159a | |
| parent | 693511033aa0eab08ea7f44ef710dcc2f590d408 (diff) | |
mb/amd/thatcher: Convert to ASL 2.0 syntax
Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46152
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/amd/thatcher/acpi/sleep.asl | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index af87ce6f89..e09a638607 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -26,20 +26,20 @@ Method(\_PTS, 1) { /* DBGO("\n") */ /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 - Store (0x07, UPWS) + UPWS = 0x07 } /* End Method(\_PTS) */ /* @@ -64,6 +64,6 @@ Method(\_WAK, 1) { /* DBGO(" to S0\n") */ /* clear USB wake up signal */ - Store(1, USBS) + USBS = 1 Return(WKST) } /* End Method(\_WAK) */ |