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authorDuncan Laurie <dlaurie@chromium.org>2012-10-08 15:26:54 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-12 04:23:30 +0100
commit2a700ec16322561ad487e6ef1ae8878f9a7e4357 (patch)
tree97edc0be8718f9cf7877a02ebf1c0e27e1626d16
parent924342bb2b9e429d66a693503c9f944655da4bb8 (diff)
SPI: Configure Software Sequence SPI Freq to match descriptor
Right now the SPI bus is getting set to 20mhz for transactions initiated with the software sequence interface. In order to be able to do reasonable fastread/write/erase we can bump this up to a higher value at boot before it gets locked at 20mhz. To do this read out the speed set in the SPI descriptor for hardware sequencing and apply it to software sequencing. Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/southbridge/intel/bd82x6x/bootblock.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 0191bbfc7f..7d0db7fba1 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -65,6 +65,26 @@ static void enable_port80_on_lpc(void)
#endif
}
+static void set_spi_speed(void)
+{
+ u32 fdod;
+ u8 ssfc;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ RCBA32(0x38b0) = 0x1000;
+
+ /* Extract the Write/Erase SPI Frequency from descriptor */
+ fdod = RCBA32(0x38b4);
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ ssfc = RCBA8(0x3893);
+ ssfc &= ~7;
+ ssfc |= fdod;
+ RCBA8(0x3893) = ssfc;
+}
+
static void bootblock_southbridge_init(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
@@ -72,6 +92,7 @@ static void bootblock_southbridge_init(void)
#endif
enable_spi_prefetch();
enable_port80_on_lpc();
+ set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);