diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2022-03-25 10:21:03 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-29 14:43:45 +0000 |
| commit | 284831e4456e770ef7f805bffaac61b1c5783564 (patch) | |
| tree | 391c4512b7b91092bbab5f0c46daf1fb04a790d3 | |
| parent | 2c3c5898f345bdb786b6306ff4b7c8f5cc6ba7cd (diff) | |
soc/amd/common/block/lpc: Add support to not clear port80 enable
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.
BUG=None
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
| -rw-r--r-- | src/soc/amd/common/block/lpc/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 5 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 64192695c6..125f8b326a 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -42,3 +42,11 @@ config SOC_AMD_COMMON_BLOCK_USE_ESPI help Select this option if mainboard uses eSPI instead of LPC (if supported by platform). + +config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN + bool + depends on SOC_AMD_COMMON_BLOCK_USE_ESPI + help + SMU will lock up at times if the port80h enable bit is cleared. Select + this option to retain the port80 enable bit while clearing other enable + bits in the ESPI Decode register. diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c61c61f8df..68d51f5ba0 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -139,7 +139,10 @@ static void espi_clear_decodes(void) unsigned int idx; /* First turn off all enable bits, then zero base, range, and size registers */ - espi_write16(ESPI_DECODE, 0); + if (CONFIG(SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN)) + espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + else + espi_write16(ESPI_DECODE, 0); for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { espi_write16(espi_io_range_base_reg(idx), 0); |