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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-08 10:26:20 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-12-09 20:52:43 +0000
commit26e384bf34d0a934e9acc4a88cd9482d78826b8b (patch)
tree7cea3383c35321383608d26bf425949a40f1dd32
parent3f5f1b5bfffc9fcb6b0b07b0e2b658ca6bd9865b (diff)
soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0
The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r--src/soc/intel/alderlake/include/soc/pci_devs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 1729160634..956a021b68 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -26,7 +26,7 @@
#endif
#define SA_DEV_SLOT_CPU_1 0x01
-#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0)
+#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0)
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)