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authorAndrey Petrov <anpetrov@fb.com>2020-04-30 14:39:37 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-05-01 23:11:44 +0000
commit26679699cddaccdc1539e5c0c4b82e49e7ec2900 (patch)
tree3bfcf4895e53e23e67562e839b3de3a82f7d9e08
parentf8f9b282b4f7ce2f6b83005db0f9aa5cf3f810ec (diff)
mb/intel/cedarisland_crb: Enable P2SB device
Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/intel/cedarisland_crb/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb
index 6eb9557484..a82f022c0b 100644
--- a/src/mainboard/intel/cedarisland_crb/devicetree.cb
+++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb
@@ -28,10 +28,10 @@ chip soc/intel/xeon_sp/cpx
device pci 17.0 on end
device pci 1c.0 on end
device pci 1c.4 on end
+ device pci 1f.1 on end
device pci 1f.2 on end
device pci 1f.4 on end
device pci 1f.5 on end
-
device pci 1f.0 on # LPC/eSPI Interface
chip superio/common
device pnp 2e.0 on