src/southbridge: Use "foo *bar" instead of "foo* bar"

Change-Id: I72d50615d77b91529810e8f590fa56f3c6f7546c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

17 files changed, 41 insertions, 37 deletions

diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
index 7b74561f3c..328818cdf2 100644
--- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
@@ -17,7 +17,7 @@
 #define AMD_PCI_INT_TYPES_H
 
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
-const char * intr_types[] = {
+const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
 	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",
@@ -27,7 +27,7 @@ const char * intr_types[] = {
 	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
 };
 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
-const char * intr_types[] = {
+const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
 	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",
diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
index 42e2b3ad8f..066c4a3e9f 100644
--- a/src/southbridge/amd/cimx/sb800/Amd.h
+++ b/src/southbridge/amd/cimx/sb800/Amd.h
@@ -61,9 +61,10 @@ typedef unsigned int AGESA_STATUS;
 #define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
 #define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
 
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2,
+				       void *ConfigPtr);
+typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr);
+typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr);
 
 ///This allocation type is used by the AmdCreateStruct entry point
 typedef enum {
diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h
index c13eda4e58..10a88f2a47 100644
--- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h
@@ -28,7 +28,7 @@
 #define NUM_IMAGE_LOCATION   32
 
 //Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+typedef void (*CIM_IMAGE_ENTRY) (void *pConfig);
 
 //Hook Call
 
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
index 854f9c3245..300969ddde 100644
--- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
+++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
@@ -16,7 +16,7 @@
 #ifndef AMD_PCI_INT_TYPES_H
 #define AMD_PCI_INT_TYPES_H
 
-const char * intr_types[] = {
+const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
 	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 29a1336f13..60d40f7049 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -50,7 +50,7 @@ static AMDSBCFG *sb_config = &sb_late_cfg;
  * @param[in] config    Southbridge configuration structure pointer.
  *
  */
-static u32 sb800_callout_entry(u32 func, u32 data, void* config)
+static u32 sb800_callout_entry(u32 func, u32 data, void *config)
 {
 	u32 ret = 0;
 	printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
index ec8140060f..c765b3371b 100644
--- a/src/southbridge/amd/cimx/sb900/Amd.h
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
@@ -61,9 +61,10 @@ typedef unsigned int AGESA_STATUS;
 #define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
 #define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
 
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2,
+				       void *ConfigPtr);
+typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr);
+typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr);
 
 ///This allocation type is used by the AmdCreateStruct entry point
 typedef enum {
diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
index c13eda4e58..10a88f2a47 100644
--- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
@@ -28,7 +28,7 @@
 #define NUM_IMAGE_LOCATION   32
 
 //Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+typedef void (*CIM_IMAGE_ENTRY) (void *pConfig);
 
 //Hook Call
 
diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
index 854f9c3245..300969ddde 100644
--- a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
@@ -16,7 +16,7 @@
 #ifndef AMD_PCI_INT_TYPES_H
 #define AMD_PCI_INT_TYPES_H
 
-const char * intr_types[] = {
+const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
 	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 158e3f4a1e..9a2f837010 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -45,7 +45,7 @@ static AMDSBCFG *sb_config = &sb_late_cfg;
  * @param[in] config    Southbridge configuration structure pointer.
  *
  */
-u32 sb900_callout_entry(u32 func, u32 data, void* config)
+u32 sb900_callout_entry(u32 func, u32 data, void *config)
 {
 	u32 ret = 0;
 
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index 2acd151252..ca76809bf3 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -26,8 +26,8 @@
 
 const struct pirq_struct * pirq_data_ptr = NULL;
 u32 pirq_data_size = 0;
-const u8 * intr_data_ptr = NULL;
-const u8 * picr_data_ptr = NULL;
+const u8 *intr_data_ptr = NULL;
+const u8 *picr_data_ptr = NULL;
 
 /*
  * Read the FCH PCI_INTR registers 0xC00/0xC01 at a
diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h
index 452db65b91..9a4695e29a 100644
--- a/src/southbridge/amd/common/amd_pci_util.h
+++ b/src/southbridge/amd/common/amd_pci_util.h
@@ -32,8 +32,8 @@ struct pirq_struct {
 
 extern const struct pirq_struct * pirq_data_ptr;
 extern u32 pirq_data_size;
-extern const u8 * intr_data_ptr;
-extern const u8 * picr_data_ptr;
+extern const u8 *intr_data_ptr;
+extern const u8 *picr_data_ptr;
 
 u8 read_pci_int_idx(u8 index, int mode);
 void write_pci_int_idx(u8 index, int mode, u8 data);
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index f8989073ea..8061bf7349 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -16,7 +16,7 @@
 #ifndef AMD_PCI_INT_TYPES_H
 #define AMD_PCI_INT_TYPES_H
 
-const char * intr_types[] = {
+const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
 	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c
index 5b2eb4c161..d3e5cfa063 100644
--- a/src/southbridge/amd/pi/hudson/gpio.c
+++ b/src/southbridge/amd/pi/hudson/gpio.c
@@ -22,7 +22,7 @@ int gpio_get(gpio_t gpio_num)
 {
 	uint32_t reg;
 
-	reg = read32((void*)(uintptr_t)gpio_num);
+	reg = read32((void *)(uintptr_t)gpio_num);
 
 	return !!(reg & GPIO_PIN_STS);
 }
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 30345bef11..43bfb02037 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -311,9 +311,9 @@ static void poweron_ddi_lanes(struct device *nb_dev)
 
 static void internal_gfx_pci_dev_init(struct device *dev)
 {
-	unsigned char * bpointer;
-	volatile u32 * GpuF0MMReg;
-	volatile u32 * pointer;
+	unsigned char *bpointer;
+	volatile u32 *GpuF0MMReg;
+	volatile u32 *pointer;
 	int i;
 	u16 command;
 	u32 value;
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index f4f33efab7..3c9393d3e3 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -187,7 +187,7 @@ static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev)
 {
 	/* NB_InitGFXStraps */
 	u32 MMIOBase, apc04, apc18, apc24, romstrap2;
-	volatile u32 * strap;
+	volatile u32 *strap;
 
 	/* Choose a base address that is unused and routed to the RS780. */
 	MMIOBase = 0xFFB00000;
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index fae26899ec..1c2fe48407 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -32,7 +32,8 @@
 /*
  * extern function declaration
  */
-struct resource * sr5650_retrieve_cpu_mmio_resource() {
+struct resource *sr5650_retrieve_cpu_mmio_resource()
+{
 	struct device *domain;
 	struct resource *res;
 
@@ -321,7 +322,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) {
 	uint32_t dword;
 	uint8_t l1_target;
 	unsigned char iommu;
-	void * mmio_base;
+	void *mmio_base;
 
 	iommu = 1;
 	get_option(&iommu, "iommu");
@@ -336,7 +337,8 @@ void detect_and_enable_iommu(struct device *iommu_dev) {
 			return;
 		}
 
-		mmio_base = (void*)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000);
+		mmio_base = (void *)(pci_read_config32(iommu_dev, 0x44) &
+				     0xffffc000);
 
 		// if (get_nb_rev(nb_dev) == REV_SR5650_A11) {
 		//	dword = pci_read_config32(iommu_dev, 0x6c);
@@ -352,11 +354,11 @@ void detect_and_enable_iommu(struct device *iommu_dev) {
 		dword |= 0x1;
 		pci_write_config32(iommu_dev, 0x44, dword);
 
-		write32((void*)(mmio_base + 0x8), 0x0);
-		write32((void*)(mmio_base + 0xc), 0x08000000);
-		write32((void*)(mmio_base + 0x10), 0x0);
-		write32((void*)(mmio_base + 0x2008), 0x0);
-		write32((void*)(mmio_base + 0x2010), 0x0);
+		write32((void *)(mmio_base + 0x8), 0x0);
+		write32((void *)(mmio_base + 0xc), 0x08000000);
+		write32((void *)(mmio_base + 0x10), 0x0);
+		write32((void *)(mmio_base + 0x2008), 0x0);
+		write32((void *)(mmio_base + 0x2010), 0x0);
 
 		/* IOMMU L1 initialization */
 		for (l1_target = 0; l1_target < 6; l1_target++) {
@@ -816,7 +818,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
+static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 {
 	uint8_t *p;
 
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index ee85124b49..a2512c95df 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -44,8 +44,8 @@ static void p64h2_ioapic_init(struct device *dev)
 	uint32_t memoryBase;
 	int apic_index, apic_id;
 
-	volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
-	volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
+	volatile uint32_t *pIndexRegister;    /* io apic io memory space command address */
+	volatile uint32_t *pWindowRegister;    /* io apic io memory space data address */
 
 	apic_index = num_p64h2_ioapics;
 	num_p64h2_ioapics++;
@@ -71,8 +71,8 @@ static void p64h2_ioapic_init(struct device *dev)
 	// NOTE: this address was assigned during enumeration of the bus
 
 	memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	pIndexRegister  = (volatile uint32_t*) memoryBase;
-	pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+	pIndexRegister  = (volatile uint32_t *) memoryBase;
+	pWindowRegister = (volatile uint32_t *)(memoryBase + 0x10);
 
 	printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
 		apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),