diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-12 16:07:43 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-16 21:00:43 +0000 |
| commit | 24d024ae24ae5f7ebd241c56ea149ade971fc663 (patch) | |
| tree | fe9098adfbec0ae98dccc898e75bf859bb63e8ab | |
| parent | 98f7d60d977e757e607a28de67aad0b3cb15d387 (diff) | |
soc/amd/cezanne: Enable ACPI_SOC_NVS
This fixes the undefined reference for NVB0, NVB1, and NVB2.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9dafe2cdb3..98c3484423 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -9,6 +9,7 @@ if SOC_AMD_CEZANNE config SOC_SPECIFIC_OPTIONS def_bool y + select ACPI_SOC_NVS select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 |