soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init

Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 65 insertions, 53 deletions

diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index b3f4fe5b2a..495f1343b7 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -201,59 +201,71 @@ static const struct reg_script pch_misc_init_script[] = {
 };
 
 /* Magic register settings for power management */
-static const struct reg_script pch_pm_init_script[] = {
-	REG_PCI_WRITE8(0xa9, 0x46),
-	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f),
-	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff),
-	REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101),
-	REG_PCI_RMW32(0xac, ~0x00200000, 0),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
+static void pch_pm_init_magic(struct device *dev)
+{
+	pci_write_config8(dev, 0xa9, 0x46);
+
+	RCBA32_AND_OR(0x232c, ~1, 0);
+
+	RCBA32_OR(0x1100, 0x0000c13f);
+
+	RCBA32_AND_OR(0x2320, ~0x60, 0x10);
+
+	RCBA32(0x3314) = 0x00012fff;
+
+	RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400);
+
+	RCBA32(0x3324) = 0x04000000;
+	RCBA32(0x3368) = 0x00041400;
+	RCBA32(0x3388) = 0x3f8ddbff;
+	RCBA32(0x33ac) = 0x00007001;
+	RCBA32(0x33b0) = 0x00181900;
+	RCBA32(0x33c0) = 0x00060A00;
+	RCBA32(0x33d0) = 0x06200840;
+	RCBA32(0x3a28) = 0x01010101;
+	RCBA32(0x3a2c) = 0x040c0404;
+	RCBA32(0x3a9c) = 0x9000000a;
+	RCBA32(0x2b1c) = 0x03808033;
+	RCBA32(0x2b34) = 0x80000009;
+	RCBA32(0x3348) = 0x022ddfff;
+	RCBA32(0x334c) = 0x00000001;
+	RCBA32(0x3358) = 0x0001c000;
+	RCBA32(0x3380) = 0x3f8ddbff;
+	RCBA32(0x3384) = 0x0001c7e1;
+	RCBA32(0x338c) = 0x0001c7e1;
+	RCBA32(0x3398) = 0x0001c000;
+	RCBA32(0x33a8) = 0x00181900;
+	RCBA32(0x33dc) = 0x00080000;
+	RCBA32(0x33e0) = 0x00000001;
+	RCBA32(0x3a20) = 0x0000040c;
+	RCBA32(0x3a24) = 0x01010101;
+	RCBA32(0x3a30) = 0x01010101;
+
+	pci_update_config32(dev, 0xac, ~0x00200000, 0);
+
+	RCBA32_OR(0x0410, 0x00000003);
+	RCBA32_OR(0x2618, 0x08000000);
+	RCBA32_OR(0x2300, 0x00000002);
+	RCBA32_OR(0x2600, 0x00000008);
+
+	RCBA32(0x33b4) = 0x00007001;
+	RCBA32(0x3350) = 0x022ddfff;
+	RCBA32(0x3354) = 0x00000001;
+
 	/* Power Optimizer */
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005),
-	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
-	REG_SCRIPT_END
-};
+	RCBA32_OR(0x33d4, 0x08000000);
+	RCBA32_OR(0x33c8, 0x00000080);
+
+	RCBA32(0x2b10) = 0x0000883c;
+	RCBA32(0x2b14) = 0x1e0a4616;
+	RCBA32(0x2b24) = 0x40000005;
+	RCBA32(0x2b20) = 0x0005db01;
+	RCBA32(0x3a80) = 0x05145005;
+	RCBA32(0x3a84) = 0x00001005;
+
+	RCBA32_OR(0x33d4, 0x2fff2fb1);
+	RCBA32_OR(0x33c8, 0x00008000);
+}
 
 static void pch_enable_mphy(void)
 {
@@ -320,7 +332,7 @@ static void pch_pm_init(struct device *dev)
 
 	pch_enable_mphy();
 
-	reg_script_run_on_dev(dev, pch_pm_init_script);
+	pch_pm_init_magic(dev);
 
 	if (pch_is_wpt()) {
 		RCBA32_OR(0x33e0, (1 << 4) | (1 << 1));