diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2018-03-26 02:25:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-28 06:44:02 +0000 |
| commit | 2410cd937925df60934855c885a16c40d2d69739 (patch) | |
| tree | 996e05982c0399a1f0e456f704bad1219be0a18b | |
| parent | 4c8fbc065874d352b2215739bae0e0ae8a04757e (diff) | |
soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.
Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 1 |
3 files changed, 8 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dab6622ac0..fc73210f75 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,6 +70,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index b2689b0608..590bb4559d 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -180,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; FSP_S_CONFIG *params = &supd->FspsConfig; - const struct device *dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; /* Parse device tree and enable/disable devices */ @@ -262,7 +263,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } - params->XdciEnable = config->XdciEnable; + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 90956c308a..2362c4255e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -124,7 +124,6 @@ struct soc_intel_cannonlake_config { /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; - uint8_t XdciEnable; uint8_t SsicPortEnable; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; |