diff options
| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2023-03-13 10:14:55 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-03-14 01:42:37 +0000 |
| commit | 23c77ef0c32f9f03a367c89babb303dde526da85 (patch) | |
| tree | a1c92f01ca78bde86e8ef634d0d757f812168f88 | |
| parent | 48286abfc1299cd2e8a71461caa34b4ea8b8e69c (diff) | |
mb/google/skyrim/var/frostflow: Update the STT settings
According to file thermal_table_0310, adjust the STT settings.
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
| -rw-r--r-- | src/mainboard/google/skyrim/variants/frostflow/overridetree.cb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index 86b1c94193..c10e0dd428 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -153,16 +153,16 @@ chip soc/amd/mendocino # STT settings register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" - register "stt_error_coeff" = "0x21" - register "stt_error_rate_coefficient" = "0x2666" - register "stt_min_limit" = "15000" - register "stt_skin_temp_apu" = "0x3000" + register "stt_error_coeff" = "0x38" + register "stt_error_rate_coefficient" = "0xbfb" + register "stt_min_limit" = "15500" + register "stt_skin_temp_apu" = "0x2b33" # STT default mode - register "stt_m1" = "0xfed2" - register "stt_m2" = "0x5f9" - register "stt_c_apu" = "0xfbf8" - register "stt_alpha_apu" = "0x4ccd" + register "stt_m1" = "0x20c" + register "stt_m2" = "0x302" + register "stt_c_apu" = "0xf7e9" + register "stt_alpha_apu" = "0x199a" # STT tablet mode register "stt_m1_tablet" = "0x208" |