AGESA: Move romstage-ramstage splitline

In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.

As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.

Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 25 insertions, 20 deletions

diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
index fc4a0b488c..54ef602d20 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/cpu/amd/agesa/romstage.c
@@ -109,15 +109,8 @@ void asmlinkage romstage_after_car(void)
 
 	fill_sysinfo(cb);
 
-	if (!HAS_LEGACY_WRAPPER) {
-		if (!cb->s3resume)
-			agesa_execute_state(cb, AMD_INIT_ENV);
-		else
-			agesa_execute_state(cb, AMD_S3LATE_RESTORE);
-	} else {
-
+	if (HAS_LEGACY_WRAPPER)
 		agesa_postcar(cb);
-	}
 
 	if (cb->s3resume)
 		set_resume_cache();
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index fbc2d7e1e5..3280180f8c 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -57,7 +57,7 @@ void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
 {
 	amd_initenv();
 #if 0
-	/* FIXME: It's only in ramstage. */
+	/* FIXME: Should move the callsite from cimx/sb800 to here. */
 	sb_Before_Pci_Init();
 #endif
 }
@@ -69,10 +69,7 @@ void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
 
 void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
 {
-#if 0
-	/* FIXME: It's only in ramstage. */
 	sb_Before_Pci_Restore_Init();
-#endif
 }
 
 void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/northbridge/amd/agesa/state_machine.c
index 0406eeea66..6892990409 100644
--- a/src/northbridge/amd/agesa/state_machine.c
+++ b/src/northbridge/amd/agesa/state_machine.c
@@ -19,6 +19,7 @@
 
 #include <arch/acpi.h>
 #include <bootstate.h>
+#include <cbmem.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -122,7 +123,9 @@ static AGESA_STATUS amd_dispatch(struct sysinfo *cb,
 			platform_AfterInitResume(cb, param);
 			break;
 		}
+#endif
 
+#if ENV_RAMSTAGE
 		case AMD_INIT_ENV:
 		{
 			AMD_ENV_PARAMS *param = (void *)StdHeader;
@@ -141,8 +144,7 @@ static AGESA_STATUS amd_dispatch(struct sysinfo *cb,
 			platform_AfterS3LateRestore(cb, param);
 			break;
 		}
-#endif
-#if ENV_RAMSTAGE
+
 		case AMD_INIT_MID:
 		{
 			AMD_MID_PARAMS *param = (void *)StdHeader;
@@ -214,6 +216,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func)
 	AMD_INTERFACE_PARAMS aip;
 	union {
 		AMD_RESET_PARAMS reset;
+		AMD_S3LATE_PARAMS s3late;
 	} agesa_params;
 	void *buf = NULL;
 	size_t len = 0;
@@ -228,7 +231,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func)
 	aip.StdHeader = cb->StdHeader;
 
 	/* For these calls, heap is not available. */
-	if (func == AMD_INIT_RESET) {
+	if (func == AMD_INIT_RESET || func == AMD_S3LATE_RESTORE) {
 		buf = (void *) &agesa_params;
 		len = sizeof(agesa_params);
 		memcpy(buf, &cb->StdHeader, sizeof(cb->StdHeader));
@@ -261,6 +264,15 @@ static void amd_bs_ramstage_init(void *arg)
 	struct sysinfo *cb = arg;
 
 	agesa_set_interface(cb);
+
+	if (!acpi_is_wakeup_s3())
+		agesa_execute_state(cb, AMD_INIT_ENV);
+	else {
+		/* We need HEAP from CBMEM early. */
+		if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
+			cbmem_initialize();
+		agesa_execute_state(cb, AMD_S3LATE_RESTORE);
+	}
 }
 
 void sb_After_Pci_Restore_Init(void);
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index e882f2e457..c3aa267c39 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -8,17 +8,20 @@
 #define AGESA_ENTRY_INIT_EARLY		TRUE
 #define AGESA_ENTRY_INIT_POST		TRUE
 
-/* Not implemented in coreboot romstage. */
-#define AGESA_ENTRY_INIT_RECOVERY	FALSE
-
 #define AGESA_ENTRY_INIT_RESUME		IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-#define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 
-/* Move to ramstage? */
+#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
 #define AGESA_ENTRY_INIT_ENV		TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#endif
 
 #else
 
+#if !IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
+#define AGESA_ENTRY_INIT_ENV		TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#endif
+
 #define AGESA_ENTRY_INIT_MID		TRUE
 #define AGESA_ENTRY_INIT_LATE		TRUE
 #define AGESA_ENTRY_INIT_S3SAVE 	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)