diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-26 21:02:33 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-28 09:46:07 +0000 |
| commit | 1f10db282878aa14985f9c7ad5cca12c04f46cc1 (patch) | |
| tree | 09067d6ad49e784b22eef9f195848bcb19d7f230 | |
| parent | abe549cac746ef535533dbb3b051d3f1dc337138 (diff) | |
mb/system76/lemp9: Relocate device enable options
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
| -rw-r--r-- | src/mainboard/system76/lemp9/devicetree.cb | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 25ae62febf..f0f5ebe3e7 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -129,9 +129,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[5]" = "5" # Misc - register "Device4Enable" = "0" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" @@ -182,7 +179,9 @@ chip soc/intel/cannonlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 04.0 off # SA Thermal device + register "Device4Enable" = "0" + end device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 @@ -198,11 +197,15 @@ chip soc/intel/cannonlake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 off # Management Engine Interface 1 + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 |