diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2022-01-21 23:34:02 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-07 14:11:17 +0000 |
| commit | 1ee6e4ab6cd147bc7adb201426039e2920c317dc (patch) | |
| tree | ba296159e1a190dfb29916114aaffb8630b231ba | |
| parent | 7e653d8451e8dd3110c8095c12efb300bff52b3b (diff) | |
mb/google/brya: Add 5G WWAN ACPI support for Brya and Redrix
Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM
features from RTD3.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
6 files changed, 47 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c0b8a34d3d..386aa11624 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -18,6 +18,7 @@ config BOARD_GOOGLE_BRYA_COMMON select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC + select DRIVERS_WWAN_FM350GL select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7cc02049a5..a277120074 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -154,8 +154,12 @@ chip soc/intel/alderlake # Enable WWAN PCIE 6 using clk 5 chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" + register "reset_delay_ms" = "1000" register "srcclk_pin" = "5" - device generic 0 on end + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on end end register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 1ef90bc764..c97ff33657 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -192,6 +192,17 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index cae22572b6..59cd8c4b40 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -189,6 +189,16 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 0cb0102c61..0698568495 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -167,6 +167,16 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 72f1da2327..fc939c7335 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -153,6 +153,16 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer |