diff options
| author | Deepika Punyamurtula <deepika.punyamurtula@intel.com> | 2020-06-12 10:49:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:50:43 +0000 |
| commit | 1e53a89f632e5384c8254f0916405d9cd19396d6 (patch) | |
| tree | ad95a05daf5892f704f9236d16ecd018e8dff0e8 | |
| parent | 103bd5e4bb14fda521f64525394b2e9232297dfd (diff) | |
mb/google/volteer: Enable thermal sensor 4 in DPTF for volteer
Enables the fourth thermal sensor for fan in DPTF for volteer
BRANCH=None
BUG=b:149722146
TEST= On volteer system check
`cat /sys/class/thermal/thermal_zone5/type` for TSR3
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl index 2e59e5e395..ddf8814312 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -38,6 +38,16 @@ #define DPTF_TSR2_ACTIVE_AC3 42 #define DPTF_TSR2_ACTIVE_AC4 39 +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor 4" +#define DPTF_TSR3_PASSIVE 65 +#define DPTF_TSR3_CRITICAL 75 +#define DPTF_TSR3_ACTIVE_AC0 50 +#define DPTF_TSR3_ACTIVE_AC1 47 +#define DPTF_TSR3_ACTIVE_AC2 45 +#define DPTF_TSR3_ACTIVE_AC3 42 +#define DPTF_TSR3_ACTIVE_AC4 39 + #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -91,6 +101,10 @@ Name (DART, Package () { Package () { \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 } }) @@ -107,6 +121,9 @@ Name (DTRT, Package () { /* CPU Throttle Effect on TSR2 sensor */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR3 sensor */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () |