diff options
| author | Nico Huber <nico.h@gmx.de> | 2023-07-07 20:19:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 13:40:01 +0000 |
| commit | 1dadb8c01d156f9cf8399976288b61a09b959ace (patch) | |
| tree | 52e524ccc190929f518a6c4d65c45fd4b0d456f3 | |
| parent | 74add29738dd9a7bafea10ae3f52217764a995bb (diff) | |
soc/intel/adl: Reduce microcode redundancy
Some of the microcode update files listed in the Makefile are redundant:
* 06-97-02 is exactly the same as 06-97-05
* 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400)
So drop these files. This saves us about 200KiB CBFS space in each case.
Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 886d532e60..f9a7c724ce 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -73,9 +73,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples -# ADL-S/HX C0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-02 -# ADL-S H0 +# ADL-S/HX C0 and ADL-S H0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 # RPL-S/HX B0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 @@ -83,9 +81,7 @@ else ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) # 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples # Missing 06-9a-02 ADL-P K0 -# ADL-P L0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-03 -# ADL-P R0 and ADL-M R0 +# ADL-P L0, ADL-P R0 and ADL-M R0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04 # RPL-P/H J0, RPL-U Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ba-02 |