diff options
| author | Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> | 2021-12-15 14:05:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-23 22:06:32 +0000 |
| commit | 1d3cff3f612bf630b7d0040deba9b1a5df20c013 (patch) | |
| tree | aebe5d766c4a92e83fad7c712611b6bba3014d88 | |
| parent | 520a4a618f117a0a8e84bef0206fdca69633ef05 (diff) | |
mb/google/hatch/var/scout: improve USB2 port 4 strength
Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram).
BUG=b:210755120
TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/scout/overridetree.cb | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index 9b33621177..07c64dbbe1 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -42,7 +42,14 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, |