Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-38

Creator:  Li-Ta Lo <ollie@lanl.gov>

emulator update

x96emu update from Paulo


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

33 files changed, 907 insertions, 883 deletions

diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h
index 855a52a61e..6967b6fb9d 100644
--- a/src/arch/i386/include/arch/acpi.h
+++ b/src/arch/i386/include/arch/acpi.h
@@ -89,7 +89,6 @@ typedef struct acpi_xsdt {
 } __attribute__ ((packed)) acpi_xsdt_t;
 
 
-
 /* HPET TIMERS */
 typedef struct acpi_hpet {
 	struct acpi_table_header header;
diff --git a/src/console/vga_console.c b/src/console/vga_console.c
index bdd56f3923..31e29f8dbb 100644
--- a/src/console/vga_console.c
+++ b/src/console/vga_console.c
@@ -10,16 +10,14 @@
 #include <pc80/vga.h>
 #include <console/console.h>
 
+//extern void beep(int ms);
+
 /* The video buffer, should be replaced by symbol in ldscript.ld */
 static char *vidmem;
 
 int vga_line, vga_col;
 
-#if CONFIG_CONSOLE_VGA == 1
 extern int vga_inited; // it will be changed in pci_rom.c
-#else
-int vga_inited = 0;
-#endif
 
 static int vga_console_inited = 0;
 
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index de4ed988c2..58a830c9b4 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -95,7 +95,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
 	if (start_mtrr >= NUM_FIXED_RANGES) {
 		return;
 	}
-	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
+	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
 		     start_mtrr, last_mtrr);
 	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
 	
diff --git a/src/devices/device.c b/src/devices/device.c
index d2c435fb72..ba4a2f4901 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -363,7 +363,6 @@ void compute_allocate_resource(
 
 
 }
-
 #if CONFIG_CONSOLE_VGA == 1
 device_t vga_pri = 0;
 static void allocate_vga_resource(void)
@@ -378,13 +377,14 @@ static void allocate_vga_resource(void)
 	vga = 0;
 	vga_onboard = 0;
 	for (dev = all_devices; dev; dev = dev->next) {
-		if (!dev->enabled) continue;
+		if ( !dev->enabled ) continue;
 		if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
 		    ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
 			if (!vga) {
 				if (dev->on_mainboard) {
 					vga_onboard = dev;
-				} else {
+				} 
+				else {
 					vga = dev;
 				}
 			}
@@ -397,8 +397,7 @@ static void allocate_vga_resource(void)
 		vga = vga_onboard;
 	}
 	
-	if (vga) {
-		// vga is first add on card or the only onboard vga
+	if (vga) { // vga is first add on card or the only onboard vga
 		printk_debug("Allocating VGA resource %s\n", dev_path(vga));
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
@@ -412,6 +411,7 @@ static void allocate_vga_resource(void)
 		bus = (bus == bus->dev->bus)? 0 : bus->dev->bus;
 	} 
 }
+
 #endif
 
 
diff --git a/src/devices/emulator/biosemu.c b/src/devices/emulator/biosemu.c
index b007ec41be..85f10c648f 100644
--- a/src/devices/emulator/biosemu.c
+++ b/src/devices/emulator/biosemu.c
@@ -161,7 +161,6 @@ void do_int(int num)
  * BIOS. Most of this information was pulled from
  * dosemu.
  */
-#if 0
 void setup_int_vect(void)
 {
 	int i;
@@ -223,7 +222,6 @@ int setup_system_bios(void *base_addr)
 
 	return 1;
 }
-#endif
 
 void reset_int_vect(void)
 {
@@ -327,8 +325,6 @@ void run_bios(struct device * dev, unsigned long addr)
 
 //	X86EMU_trace_on();
 
-	printk_info("entering emulator\n");
-
 	X86EMU_exec();
 #endif
 }
diff --git a/src/devices/emulator/x86emu/debug.c b/src/devices/emulator/x86emu/debug.c
index e25229a689..dd47e3d3a5 100644
--- a/src/devices/emulator/x86emu/debug.c
+++ b/src/devices/emulator/x86emu/debug.c
@@ -225,7 +225,6 @@ void X86EMU_dump_memory (u16 seg, u16 off, u32 amt)
 
 void x86emu_single_step (void)
 {
-#if 0
     char s[1024];
     int ps[10];
     int ntok;
@@ -314,7 +313,6 @@ void x86emu_single_step (void)
             break;
         }
     }
-#endif
 }
 
 int X86EMU_trace_on(void)
@@ -329,7 +327,6 @@ int X86EMU_trace_off(void)
 
 static int parse_line (char *s, int *ps, int *n)
 {
-#if 0
     int cmd;
 
     *n = 0;
@@ -355,7 +352,6 @@ static int parse_line (char *s, int *ps, int *n)
         sscanf(s,"%x",&ps[*n]);
         *n += 1;
     }
-#endif
 }
 
 #endif /* DEBUG */
diff --git a/src/devices/emulator/x86emu/decode.c b/src/devices/emulator/x86emu/decode.c
index e7010fe579..1badb2db7c 100644
--- a/src/devices/emulator/x86emu/decode.c
+++ b/src/devices/emulator/x86emu/decode.c
@@ -77,8 +77,6 @@ next instruction.
 void x86emu_intr_raise(
     u8 intrnum)
 {
-    printk("%s, rasing execption %x\n", __func__, intrnum);
-    x86emu_dump_regs();
     M.x86.intno = intrnum;
     M.x86.intr |= INTR_SYNCH;
 }
diff --git a/src/devices/emulator/x86emu/ops.c b/src/devices/emulator/x86emu/ops.c
index 4666e93ff4..2534b65863 100644
--- a/src/devices/emulator/x86emu/ops.c
+++ b/src/devices/emulator/x86emu/ops.c
@@ -70,7 +70,7 @@
 *
 ****************************************************************************/
 
-#include "x86emu/x86emui.h"
+#include "x86emui.h"
 
 /*----------------------------- Implementation ----------------------------*/
 
@@ -219,8 +219,7 @@ void x86emuOp_genop_byte_RM_R(u8 op1)
         DECODE_PRINTF("\n");
         TRACE_AND_STEP();
         destval = genop_byte_operation[op1](destval, *srcreg);
-        if (op1 != 7)
-            store_data_byte(destoffset, destval);
+        store_data_byte(destoffset, destval);
         }
     else
         {                       /* register to register */
@@ -263,8 +262,7 @@ void x86emuOp_genop_word_RM_R(u8 op1)
             DECODE_PRINTF("\n");
             TRACE_AND_STEP();
             destval = genop_long_operation[op1](destval, *srcreg);
-            if (op1 != 7)
-                store_data_long(destoffset, destval);
+            store_data_long(destoffset, destval);
         } else {
             u16 destval;
             u16 *srcreg;
@@ -275,12 +273,11 @@ void x86emuOp_genop_word_RM_R(u8 op1)
             DECODE_PRINTF("\n");
             TRACE_AND_STEP();
             destval = genop_word_operation[op1](destval, *srcreg);
-            if (op1 != 7)
-                store_data_word(destoffset, destval);
+            store_data_word(destoffset, destval);
         }
     } else {                    /* register to register */
         if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg, *srcreg;
+            u32 *destreg,*srcreg;
 
             destreg = DECODE_RM_LONG_REGISTER(rl);
             DECODE_PRINTF(",");
@@ -289,7 +286,7 @@ void x86emuOp_genop_word_RM_R(u8 op1)
             TRACE_AND_STEP();
             *destreg = genop_long_operation[op1](*destreg, *srcreg);
         } else {
-            u16 *destreg, *srcreg;
+            u16 *destreg,*srcreg;
 
             destreg = DECODE_RM_WORD_REGISTER(rl);
             DECODE_PRINTF(",");
@@ -1335,7 +1332,9 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
         imm = fetch_byte_imm();
         DECODE_PRINTF2("%x\n", imm);
         TRACE_AND_STEP();
-        *destreg = (*genop_byte_operation[rh]) (*destreg, imm);
+        destval = (*genop_byte_operation[rh]) (*destreg, imm);
+        if (rh != 7)
+            *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1424,23 +1423,29 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
         }
     } else {                     /* register to register */
         if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg, imm;
+            u32 *destreg;
+            u32 destval,imm;
 
             destreg = DECODE_RM_LONG_REGISTER(rl);
             DECODE_PRINTF(",");
             imm = fetch_long_imm();
             DECODE_PRINTF2("%x\n", imm);
             TRACE_AND_STEP();
-            *destreg = (*genop_long_operation[rh]) (*destreg, imm);
+            destval = (*genop_long_operation[rh]) (*destreg, imm);
+            if (rh != 7)
+                *destreg = destval;
         } else {
-            u16 *destreg, imm;
+            u16 *destreg;
+            u16 destval,imm;
 
             destreg = DECODE_RM_WORD_REGISTER(rl);
             DECODE_PRINTF(",");
             imm = fetch_word_imm();
             DECODE_PRINTF2("%x\n", imm);
             TRACE_AND_STEP();
-            *destreg = (*genop_word_operation[rh]) (*destreg, imm);
+            destval = (*genop_word_operation[rh]) (*destreg, imm);
+            if (rh != 7)
+                *destreg = destval;
         }
     }
     DECODE_CLEAR_SEGOVR();
@@ -1518,7 +1523,9 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
         imm = fetch_byte_imm();
         DECODE_PRINTF2(",%x\n", imm);
         TRACE_AND_STEP();
-        *destreg = (*genop_byte_operation[rh]) (*destreg, imm);
+        destval = (*genop_byte_operation[rh]) (*destreg, imm);
+        if (rh != 7)
+            *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1604,21 +1611,27 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
         }
     } else {                     /* register to register */
         if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg, imm;
+            u32 *destreg;
+            u32 destval,imm;
 
             destreg = DECODE_RM_LONG_REGISTER(rl);
             imm = (s8) fetch_byte_imm();
             DECODE_PRINTF2(",%x\n", imm);
             TRACE_AND_STEP();
-            *destreg = (*genop_long_operation[rh]) (*destreg, imm);
+            destval = (*genop_long_operation[rh]) (*destreg, imm);
+            if (rh != 7)
+                *destreg = destval;
         } else {
-            u16 *destreg, imm;
+            u16 *destreg;
+            u16 destval,imm;
 
             destreg = DECODE_RM_WORD_REGISTER(rl);
             imm = (s8) fetch_byte_imm();
             DECODE_PRINTF2(",%x\n", imm);
             TRACE_AND_STEP();
-            *destreg = (*genop_word_operation[rh]) (*destreg, imm);
+            destval = (*genop_word_operation[rh]) (*destreg, imm);
+            if (rh != 7)
+                *destreg = destval;
         }
     }
     DECODE_CLEAR_SEGOVR();
diff --git a/src/devices/emulator/x86emu/ops2.c b/src/devices/emulator/x86emu/ops2.c
index 448d968570..6afd36e2e9 100644
--- a/src/devices/emulator/x86emu/ops2.c
+++ b/src/devices/emulator/x86emu/ops2.c
@@ -61,7 +61,7 @@ void x86emuOp2_illegal_op(
     END_OF_INSTR();
 }
 
-#define xorl(a,b)   (((a) && !(b)) || (!(a) && (b)))
+#define xorl(a,b)   ((a) && !(b)) || (!(a) && (b))
 
 /****************************************************************************
 REMARKS:
diff --git a/src/devices/emulator/x86emu/prim_ops.c b/src/devices/emulator/x86emu/prim_ops.c
index fa19cb4844..a707521d49 100644
--- a/src/devices/emulator/x86emu/prim_ops.c
+++ b/src/devices/emulator/x86emu/prim_ops.c
@@ -1921,7 +1921,7 @@ Implements the IMUL instruction and side effects.
 void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
 {
 #ifdef  __HAS_LONG_LONG__
-    s64 res = (s64)d * (s64)s;
+    s64 res = (s32)d * (s32)s;
 
     *res_lo = (u32)res;
     *res_hi = (u32)(res >> 32);
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index ac2e413cc0..e0a7138464 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -53,7 +53,7 @@ struct rom_header * pci_rom_probe(struct device *dev)
 	if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
 		printk_err("Class Code mismatch ROM %08x, dev %08x\n", 
 			    (rom_data->class_hi << 8) | rom_data->class_lo, dev->class);
-		//return NULL;
+//		return NULL;
 	}
 
 	return rom_header;
@@ -62,8 +62,8 @@ struct rom_header * pci_rom_probe(struct device *dev)
 static void *pci_ram_image_start = PCI_RAM_IMAGE_START;
 
 #if CONFIG_CONSOLE_VGA == 1
-int vga_inited = 0;		// used by vga_console.c 
-extern device_t vga_pri;	// the primary vga device, defined in device.c
+int vga_inited = 0; // it will be used by vga_console 
+extern device_t vga_pri; // The only VGA
 #endif
 
 struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header)
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index a9df17bcdf..5d065fa4cf 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -129,61 +129,48 @@ config chip.h
 
 # config for arima/hdama
 chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
 	device pci_domain 0 on
 		chip northbridge/amd/amdk8
 			device pci 18.0 on #  northbridge 
 				#  devices on link 0, link 0 == LDT 0 
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
-					device pci 0.0 on end	# PCIX bridge
-					device pci 0.1 on end	# IOAPIC
-					device pci 1.0 on end	# PCIX bridge
-					device pci 1.1 on end	# IOAPIC 
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
 				end
 				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent of the next one
+					# this "device pci 0.0" is the parent the next one
 					# PCI bridge
 					device pci 0.0 on
-						device pci 0.0 on  end # USB0
-						device pci 0.1 on  end # USB1
-						device pci 0.2 off end # USB 2.0
-						device pci 1.0 off end # LAN
-						chip drivers/pci/onboard
-							device pci 6.0 on end # ATI Rage XL
-							register "rom_address" = "0xfff80000"
-						end
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
 					end
-					# LPC bridge
 					device pci 1.0 on
 						chip superio/NSC/pc87360
-							device	pnp 2e.0 off	# Floppy 
+							device	pnp 2e.0 off  # Floppy 
 								 io 0x60 = 0x3f0
 								irq 0x70 = 6
 								drq 0x74 = 2
 							end
-							device pnp 2e.1 off	# Parallel Port
+							device pnp 2e.1 off  # Parallel Port
 								 io 0x60 = 0x378
 								irq 0x70 = 7
 							end
-							device pnp 2e.2 off	# Com 2
+							device pnp 2e.2 off # Com 2
 								 io 0x60 = 0x2f8
 								irq 0x70 = 3
 							end
-							device pnp 2e.3 on	# Com 1
+							device pnp 2e.3 on  # Com 1
 								 io 0x60 = 0x3f8
 								irq 0x70 = 4
 							end
 							device pnp 2e.4 off end # SWC
 							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on	# Keyboard
+							device pnp 2e.6 on  # Keyboard
 								 io 0x60 = 0x60
 								 io 0x62 = 0x64
 								irq 0x70 = 1
@@ -194,9 +181,9 @@ chip northbridge/amd/amdk8/root_complex
 							device pnp 2e.a off end # WDT  
 						end
 					end
-					device pci 1.1 on end	# IDE
-					device pci 1.2 on end	# SMBus 2.0
-					device pci 1.3 on 	# System Management
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on 
 						chip drivers/generic/generic
 							#phillips pca9545 smbus mux
 							device i2c 70 on 
@@ -234,19 +221,19 @@ chip northbridge/amd/amdk8/root_complex
 							device i2c 57 on end
 						end 
 					end
-					device pci 1.5 off end	# AC97 Audio
-					device pci 1.6 on  end	# AC97 Modem
+					device pci 1.5 off end
+					device pci 1.6 on end
 					register "ide0_enable" = "1"
 					register "ide1_enable" = "1"
 				end
-			end # device pci 18.0 
+			end #  device pci 18.0 
 			
 			device pci 18.0 on end # LDT1
 			device pci 18.0 on end # LDT2
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
-		end  # chip northbridge/amd/amdk8
+		end
 		chip northbridge/amd/amdk8
 			device pci 19.0 on end
 			device pci 19.0 on end
@@ -255,6 +242,14 @@ chip northbridge/amd/amdk8/root_complex
 			device pci 19.2 on end
 			device pci 19.3 on end
 		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
 	end
 end
 
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
index 1972c39fe4..091f792e3b 100644
--- a/src/mainboard/arima/hdama/Options.lb
+++ b/src/mainboard/arima/hdama/Options.lb
@@ -50,8 +50,6 @@ uses CROSS_COMPILE
 uses CC
 uses HOSTCC
 uses OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
 
 ###
 ### Build options
@@ -121,10 +119,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
 ##
 default CONFIG_IOAPIC=1
 
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
 ##
 ## Clean up the motherboard id strings
 ##
diff --git a/src/mainboard/ibm/e325/auto.c b/src/mainboard/ibm/e325/auto.c
index b1c9e772d5..dbbcbf597b 100644
--- a/src/mainboard/ibm/e325/auto.c
+++ b/src/mainboard/ibm/e325/auto.c
@@ -158,21 +158,16 @@ static void main(unsigned long bist)
 	};
 
 	int needs_reset;
-        unsigned nodeid;
-
 	if (bist == 0) {
 		/* Skip this if there was a built in self test failure */
 		amd_early_mtrr_init();
 		enable_lapic();
 		init_timer();
-
-                nodeid = lapicid() & 0xf;
-
 		/* Has this cpu already booted? */
-		if (cpu_init_detected(nodeid)) {
+		if (cpu_init_detected()) {
 			asm volatile ("jmp __cpu_reset");
 		}
-		distinguish_cpu_resets(nodeid);
+		distinguish_cpu_resets();
 		if (!boot_cpu()) {
 			stop_this_cpu();
 		}
diff --git a/src/mainboard/ibm/e325/failover.c b/src/mainboard/ibm/e325/failover.c
index ed5ce32d81..e351cae83d 100644
--- a/src/mainboard/ibm/e325/failover.c
+++ b/src/mainboard/ibm/e325/failover.c
@@ -13,14 +13,11 @@
 
 static unsigned long main(unsigned long bist)
 {
-        unsigned nodeid;
 	/* Make cerain my local apic is useable */
 	enable_lapic();
 
-        nodeid = lapicid() & 0xf;
-
 	/* Is this a cpu only reset? */
-	if (cpu_init_detected(nodeid)) {
+	if (cpu_init_detected()) {
 		if (last_boot_normal()) {
 			goto normal_image;
 		} else {
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index 96c543a1ec..448d86fb09 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -125,64 +125,61 @@ dir /pc80
 config chip.h
 
 chip northbridge/via/vt8601
-	device pci_domain 0 on
-    		device pci 0.0 on end			# Northbridge
-		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
-		end
-		chip southbridge/via/vt8231
-			register "enable_native_ide" = "0"
-			register "enable_com_ports" = "1"
-			register "enable_keyboard" = "0"
-			device pci 11.0 on              # Southbrdge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 on      #  Floppy
-					   io 0x60 = 0x3f0
-					  irq 0x70 = 6
-					  drq 0x74 = 2
-					end
-					device pnp 2e.1 off     #  Parallel Port
-					   io 0x60 = 0x378
-					  irq 0x70 = 7
-					end
-					device pnp 2e.2 on      #  Com1
-					   io 0x60 = 0x3f8
-					  irq 0x70 = 4
-					end
-					device pnp 2e.3 off     #  Com2
-					   io 0x60 = 0x2f8
-					  irq 0x70 = 3
-					end
-					device pnp 2e.5 on      #  Keyboard
-					   io 0x60 = 0x60
-					   io 0x62 = 0x64
-					  irq 0x70 = 1
-					  irq 0x72 = 12
-	      				end
-				register "com1" = "{1}"
-				end
-				device pnp 2e.6 off end 	#  CIR
-				device pnp 2e.7 off end 	#  GAME_MIDI_GIPO1
-				device pnp 2e.8 off end		#  GPIO2
-				device pnp 2e.9 off end 	#  GPIO3
-				device pnp 2e.a off end		#  ACPI
-				device pnp 2e.b on		#  HW Monitor
-					io 0x60 = 0x290
-				end
-			end
-			device pci 11.1 on  end		# Ide
-			device pci 11.2 off end		# Usb port 0-1
-			device pci 11.3 off end		# Usb port 2-3
-			device pci 11.4 off end		# ACPI
-			device pci 11.5 off end		# AC97 Audio
-			device pci 11.6 on  end		# AC97 Modem
-          		device pci 12.0 on  end		# Ethernet
-        	end
-	end
-
-	chip cpu/via/model_centaur 
-  	end
+  device pci_domain 0 on
+    device pci 0.0 on
+      chip southbridge/via/vt8231
+        register "enable_usb" = "0"
+        register "enable_native_ide" = "0"
+        register "enable_com_ports" = "1"
+        register "enable_keyboard" = "0"
+        register "enable_nvram" = "1"
+        device pci 11.0 on            # Southbridge
+          device pci 11.1 on  end       # Ide
+          device pci 11.2 off end       # Usb
+          device pci 11.3 off end       # Usb
+          device pci 11.4 off end       # ACPI
+          device pci 11.5 off end       # Audio
+          device pci 11.6 on            # Com
+            chip superio/winbond/w83627hf
+              device pnp 2e.0 on      #  Floppy
+                 io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 off     #  Parallel Port
+                 io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 2e.2 on      #  Com1
+                 io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off     #  Com2
+                 io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 on      #  Keyboard
+                 io 0x60 = 0x60
+                 io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x72 = 12
+              end
+              device pnp 2e.6 off end #  CIR
+              device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+              device pnp 2e.8 off end #  GPIO2
+              device pnp 2e.9 off end #  GPIO3
+              device pnp 2e.a off end #  ACPI
+              device pnp 2e.b on      #  HW Monitor
+                 io 0x60 = 0x290
+              end
+              register "com1" = "{1}"
+            end
+          end
+          device pci 12.0 on end        # Ethernet
+        end
+      end
+    end
+  end
+  chip cpu/via/model_centaur 
+  end
 end
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
index 259acfbc24..d8d3490dd0 100644
--- a/src/mainboard/via/epia/Options.lb
+++ b/src/mainboard/via/epia/Options.lb
@@ -1,10 +1,3 @@
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
@@ -47,18 +40,6 @@ uses MAXIMUM_CONSOLE_LOGLEVEL
 uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 
-default CONFIG_CONSOLE_SERIAL8250=1
-## Select the serial console baud rate
-default TTYS0_BAUD=19200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-                                                                                
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-default CONFIG_CHIP_NAME=1
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
 
diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c
index 9e12f52a7c..6c8ea903ee 100644
--- a/src/mainboard/via/epia/auto.c
+++ b/src/mainboard/via/epia/auto.c
@@ -2,6 +2,9 @@
 
 #include <stdint.h>
 #include <device/pci_def.h>
+#if 0
+#include <cpu/x86/lapic.h>
+#endif
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
@@ -18,7 +21,7 @@
 void udelay(int usecs) 
 {
 	int i;
-	for (i = 0; i < usecs; i++)
+	for(i = 0; i < usecs; i++)
 		outb(i&0xff, 0x80);
 }
 
@@ -27,8 +30,18 @@ void udelay(int usecs)
 #include "debug.c"
 
 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
+
+
 #include "southbridge/via/vt8231/vt8231_early_serial.c"
+static void memreset_setup(void)
+{
+}
 
+/*
+  static void memreset(int controllers, const struct mem_controller *ctrl)
+  {
+  }
+*/
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	unsigned char c;
@@ -36,6 +49,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return c;
 }
 
+
+
 #include "northbridge/via/vt8601/raminit.c"
 /*
   #include "sdram/generic_sdram.c"
@@ -51,7 +66,6 @@ static void enable_mainboard_devices(void)
 	if (dev == PCI_DEV_INVALID) {
 		die("Southbridge not found!!!\n");
 	}
-
 	pci_write_config8(dev, 0x50, 7);
 	pci_write_config8(dev, 0x51, 0xff);
 #if 0
@@ -73,9 +87,9 @@ static void enable_mainboard_devices(void)
 
 static void enable_shadow_ram(void) 
 {
-	device_t dev = 0;
+	device_t dev = 0; /* no need to look up 0:0.0 */
 	unsigned char shadowreg;
-
+	/* dev 0 for southbridge */
 	shadowreg = pci_read_config8(dev, 0x63);
 	/* 0xf0000-0xfffff */
 	shadowreg |= 0x30;
@@ -99,8 +113,8 @@ static void main(unsigned long bist)
 	enable_mainboard_devices();
 	enable_smbus();
 	enable_shadow_ram();
-
 	/*
+	  memreset_setup();
 	  this is way more generic than we need.
 	  sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 	*/
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index cf8e82907c..b578a975e4 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -29,6 +29,8 @@ static void northbridge_init(device_t dev)
 	pci_write_config8(dev, 0x76, 0x52);
 }
 
+
+
 static struct device_operations northbridge_operations = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
@@ -44,6 +46,8 @@ static struct pci_driver northbridge_driver __pci_driver = {
 	.device = 0x0601, /* 0x8601 is the AGP bridge? */
 };
 
+
+
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
 static void pci_domain_read_resources(device_t dev)
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index 1aa58224f7..71ac010156 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -47,30 +47,32 @@ it with the version available from LANL.
 #define DIMM_CL2 0
 #endif
 
-void dimms_read(unsigned long x)
+void dimms_read(unsigned long x) 
 {
 	uint8_t c;
-	unsigned long eax;
+	unsigned long eax; 
 	volatile unsigned long y;
-	eax = x;
-	for (c = 0; c < 6; c++) {
-		y = *(volatile unsigned long *) eax;
+	eax =  x;
+	for(c = 0; c < 6; c++) {
+		y = * (volatile unsigned long *) eax;
 		eax += 0x10000000;
 	}
 }
 
-void dimms_write(int x)
+void dimms_write(int x) 
 {
 	uint8_t c;
 	unsigned long eax = x;
-	for (c = 0; c < 6; c++) {
+	for(c = 0; c < 6; c++) {
 		*(volatile unsigned long *) eax = 0;
 		eax += 0x10000000;
 	}
 }
 
+
+
 #ifdef DEBUG_SETNORTHB
-void setnorthb(device_t north, uint8_t reg, uint8_t val)
+void setnorthb(device_t north, uint8_t reg, uint8_t val) 
 {
 	print_debug("setnorth: reg ");
 	print_debug_hex8(reg);
@@ -83,108 +85,108 @@ void setnorthb(device_t north, uint8_t reg, uint8_t val)
 #define setnorthb pci_write_config8
 #endif
 
-void dumpnorth(device_t north)
+void
+dumpnorth(device_t north) 
 {
 	unsigned int r, c;
-	for (r = 0;; r += 16) {
+	for(r = 0; ; r += 16) {
 		print_debug_hex8(r);
 		print_debug(":");
-		for (c = 0; c < 16; c++) {
-			print_debug_hex8(pci_read_config8(north, r + c));
+		for(c = 0; c < 16; c++) {
+			print_debug_hex8(pci_read_config8(north, r+c));
 			print_debug(" ");
 		}
 		print_debug("\r\n");
 		if (r >= 240)
 			break;
-	}
+  }
 }
 
-static void sdram_set_registers(const struct mem_controller *ctrl)
+static void sdram_set_registers(const struct mem_controller *ctrl) 
 {
-	device_t north = (device_t) PCI_DEV(0, 0, 0);
+	device_t north = (device_t) 0;
 	uint8_t c, r;
 
 	print_err("vt8601 init starting\r\n");
+	north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
+	north = 0;
 	print_debug_hex32(north);
 	print_debug(" is the north\n");
 	print_debug_hex16(pci_read_config16(north, 0));
 	print_debug(" ");
 	print_debug_hex16(pci_read_config16(north, 2));
 	print_debug("\r\n");
-
+	
 	/* All we are doing now is setting initial known-good values that will
 	 * be revised later as we read SPD
-	 */
-
+	 */	
 	// memory clk enable. We are not using ECC
-	pci_write_config8(north, 0x78, 0x01);
+	pci_write_config8(north,0x78, 0x01);
 	print_debug_hex8(pci_read_config8(north, 0x78));
-
 	// dram control, see the book. 
 #if DIMM_PC133
-	pci_write_config8(north, 0x68, 0x52);
+	pci_write_config8(north,0x68, 0x52);
 #else
-	pci_write_config8(north, 0x68, 0x42);
+	pci_write_config8(north,0x68, 0x42);
 #endif
-
 	// dram control, see the book. 
-	pci_write_config8(north, 0x6B, 0x0c);
-
+	pci_write_config8(north,0x6B, 0x0c);
 	// Initial setting, 256MB in each bank, will be rewritten later.
-	pci_write_config8(north, 0x5A, 0x20);
+	pci_write_config8(north,0x5A, 0x20);
 	print_debug_hex8(pci_read_config8(north, 0x5a));
-	pci_write_config8(north, 0x5B, 0x40);
-	pci_write_config8(north, 0x5C, 0x60);
-	pci_write_config8(north, 0x5D, 0x80);
-	pci_write_config8(north, 0x5E, 0xA0);
-	pci_write_config8(north, 0x5F, 0xC0);
+	pci_write_config8(north,0x5B, 0x40);
+	pci_write_config8(north,0x5C, 0x60);
+	pci_write_config8(north,0x5D, 0x80);
+	pci_write_config8(north,0x5E, 0xA0);
+	pci_write_config8(north,0x5F, 0xC0);
 	// It seems we have to take care of these 2 registers as if 
 	// they are bank 6 and 7.
-	pci_write_config8(north, 0x56, 0xC0);
-	pci_write_config8(north, 0x57, 0xC0);
-
+	pci_write_config8(north,0x56, 0xC0);
+	pci_write_config8(north,0x57, 0xC0);
+	
 	// SDRAM in all banks
-	pci_write_config8(north, 0x60, 0x3F);
-
+	pci_write_config8(north,0x60, 0x3F);
 	// DRAM timing. I'm suspicious of this
 	// This is for all banks, 64 is 0,1.  65 is 2,3. 66 is 4,5.
 	// ras precharge 4T, RAS pulse 5T
 	// cas2 is 0xd6, cas3 is 0xe6
 	// we're also backing off write pulse width to 2T, so result is 0xee
 #if DIMM_CL2
-	pci_write_config8(north, 0x64, 0xd4);
-	pci_write_config8(north, 0x65, 0xd4);
-	pci_write_config8(north, 0x66, 0xd4);
-#else				// CL=3
-	pci_write_config8(north, 0x64, 0xe4);
-	pci_write_config8(north, 0x65, 0xe4);
-	pci_write_config8(north, 0x66, 0xe4);
+	pci_write_config8(north,0x64, 0xd4);
+	pci_write_config8(north,0x65, 0xd4);
+	pci_write_config8(north,0x66, 0xd4);
+#else // CL=3
+	pci_write_config8(north,0x64, 0xe4);
+	pci_write_config8(north,0x65, 0xe4);
+	pci_write_config8(north,0x66, 0xe4);
 #endif
 
 	// dram frequency select.
 	// enable 4K pages for 64M dram. 
 #if DIMM_PC133
-	pci_write_config8(north, 0x69, 0x3c);
+	pci_write_config8(north,0x69, 0x3c);
 #else
-	pci_write_config8(north, 0x69, 0xac);
+	pci_write_config8(north,0x69, 0xac);
 #endif
 
 	/* IMPORTANT -- disable refresh counter */
 	// refresh counter, disabled.
-	pci_write_config8(north, 0x6A, 0x00);
+	pci_write_config8(north,0x6A, 0x00);
+	
 
 	// clkenable configuration. kevinh FIXME - add precharge
-	pci_write_config8(north, 0x6C, 0x00);
+	pci_write_config8(north,0x6C, 0x00);
 	// dram read latch delay of 1 ns, MD drive 8 mA,
-	// high drive strength on MA[2: 13], we#, cas#, ras#
+	// high drive strength on MA[2:	13], we#, cas#, ras#
 	// As per Cindy Lee, set to 0x37, not 0x57
-	pci_write_config8(north, 0x6D, 0x7f);
+	pci_write_config8(north,0x6D, 0x7f);
 }
 
 /* slot is the dram slot. Return size of side0 in lower 16-bit,
  * side1 in upper 16-bit, in units of 8MB */
-static unsigned long spd_module_size(unsigned char slot)
-{
+static unsigned long 
+spd_module_size(unsigned char slot) 
+{ 
 	/* for all the DRAMS, see if they are there and get the size of each
 	 * module. This is just a very early first cut at sizing.
 	 */
@@ -193,24 +195,21 @@ static unsigned long spd_module_size(unsigned char slot)
 	unsigned int value = 0;
 	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
-
 	/* is the module there? if byte 2 is not 4, then we'll assume it 
 	 * is useless. 
 	 */
-	print_info("Slot ");
-	print_info_hex8(slot);
+	print_info("Slot "); 
+	print_info_hex8(slot); 
 	if (smbus_read_byte(module, 2) != 4) {
 		print_info(" is empty\r\n");
 		return 0;
 	}
 	print_info(" is SDRAM ");
-
+	
 	banks = smbus_read_byte(module, 17);
-
 	/* we're going to assume symmetric banks. Sorry. */
-	cols = smbus_read_byte(module, 4) & 0xf;
-	rows = smbus_read_byte(module, 3) & 0xf;
-
+	cols = smbus_read_byte(module, 4)  & 0xf;
+	rows = smbus_read_byte(module, 3)  & 0xf;
 	/* grand total. You have rows+cols addressing, * times of banks, times
 	 * width of data in bytes */
 	/* Width is assumed to be 64 bits == 8 bytes */
@@ -230,8 +229,10 @@ static unsigned long spd_module_size(unsigned char slot)
 
 }
 
-static int spd_num_chips(unsigned char slot)
-{
+static int
+spd_num_chips(unsigned char slot) 
+{ 
+/*	unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
 	unsigned int width;
 
@@ -248,21 +249,20 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	unsigned char timing = 0xe4;
 	/* read Trp */
 	val = smbus_read_byte(0x50, 27);
-	if (val < 2 * T133)
+	if (val < 2*T133)
 		Trp = 1;
 	val = smbus_read_byte(0x50, 30);
-	if (val < 5 * T133)
+	if (val < 5*T133)
 		Tras = 0;
 	val = smbus_read_byte(0x50, 18);
 	if (val < 8)
 		casl = 1;
 	if (val < 4)
 		casl = 0;
-
+	
 	val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
-
-	print_debug_hex8(val);
-	print_debug(" is the computed timing\n");
+	
+	print_debug_hex8(val); print_debug(" is the computed timing\n");
 	/* don't set it. Experience shows that this screwy chipset should just
 	 * be run with the most conservative timing.
 	 * pci_write_config8(0, 0x64, val);
@@ -271,23 +271,23 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 
 static void set_ma_mapping(device_t north, int slot, int type)
 {
-	unsigned char reg, val;
-	int shift;
-
-	reg = 0x58 + slot / 2;
-	if (slot % 2 >= 1)
-		shift = 0;
-	else
-		shift = 4;
-
-	val = pci_read_config8(north, reg);
-	val &= ~(0xf << shift);
-	val |= type << shift;
-	pci_write_config8(north, reg, val);
+    unsigned char reg, val;
+    int shift;
+
+    reg = 0x58 + slot/2;
+    if (slot%2 >= 1)
+        shift = 0;
+    else
+        shift = 4;
+
+    val = pci_read_config8(north, reg);
+    val &= ~(0xf << shift);
+    val |= type << shift;
+    pci_write_config8(north, reg, val);
 }
 
 
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+static void sdram_enable(int controllers, const struct mem_controller *ctrl) 
 {
 	unsigned char i;
 	static const uint8_t ramregs[] = {
@@ -295,30 +295,29 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	};
 	device_t north = 0;
 	uint32_t size, base, slot, ma;
-	/* begin to initialize */
-
+	/* begin to initialize*/
 	// I forget why we need this, but we do
 	dimms_write(0xa55a5aa5);
-
-	/* set NOP */
-	pci_write_config8(north, 0x6C, 0x01);
+	
+	/* set NOP*/
+	pci_write_config8(north,0x6C, 0x01);
 	print_debug("NOP\r\n");
-	/* wait 200us */
+	/* wait 200us*/
 	// You need to do the memory reference. That causes the nop cycle. 
 	dimms_read(0);
 	udelay(400);
 	print_debug("PRECHARGE\r\n");
 	/* set precharge */
-	pci_write_config8(north, 0x6C, 0x02);
+	pci_write_config8(north,0x6C, 0x02);
 	print_debug("DUMMY READS\r\n");
-	/* dummy reads */
+	/* dummy reads*/
 	dimms_read(0);
 	udelay(200);
 	print_debug("CBR\r\n");
-	/* set CBR */
-	pci_write_config8(north, 0x6C, 0x04);
-
-	/* do 8 reads and wait >100us between each - from via */
+	/* set CBR*/
+	pci_write_config8(north,0x6C, 0x04);
+	
+	/* do 8 reads and wait >100us between each - from via*/
 	dimms_read(0);
 	udelay(200);
 	dimms_read(0);
@@ -336,43 +335,43 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	dimms_read(0);
 	udelay(200);
 	print_debug("MRS\r\n");
-	/* set MRS */
-	pci_write_config8(north, 0x6c, 0x03);
+	/* set MRS*/
+	pci_write_config8(north,0x6c, 0x03);
 #if DIMM_CL2
 	dimms_read(0x150);
-#else				// CL=3
+#else // CL=3
 	dimms_read(0x1d0);
 #endif
 	udelay(200);
 	print_debug("NORMAL\r\n");
 	/* set to normal mode */
-	pci_write_config8(north, 0x6C, 0x08);
-
+	pci_write_config8(north,0x6C, 0x08);
+	
 	dimms_write(0x55aa55aa);
 	dimms_read(0);
 	udelay(200);
 	print_debug("set ref. rate\r\n");
 	// Set the refresh rate. 
 #if DIMM_PC133
-	pci_write_config8(north, 0x6A, 0x86);
+	pci_write_config8(north,0x6A, 0x86);
 #else
-	pci_write_config8(north, 0x6A, 0x65);
+	pci_write_config8(north,0x6A, 0x65);
 #endif
 	print_debug("enable multi-page open\r\n");
 	// enable multi-page open
-	pci_write_config8(north, 0x6B, 0x0d);
-
+	pci_write_config8(north,0x6B, 0x0d);
+	
 	base = 0;
-	for (slot = 0; slot < 4; slot++) {
+	for(slot = 0; slot < 4; slot++) {
 		size = spd_module_size(slot);
 		/* side 0 */
 		base += size & 0xffff;
-		pci_write_config8(north, ramregs[2 * slot], base);
+		pci_write_config8(north, ramregs[2*slot], base);
 		/* side 1 */
 		base += size >> 16;
 		if (base > 0xff)
 			base = 0xff;
-		pci_write_config8(north, ramregs[2 * slot + 1], base);
+		pci_write_config8(north, ramregs[2*slot + 1], base);
 
 		if (!size)
 			continue;
@@ -380,13 +379,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		/* Calculate the value of MA mapping type register,
 		 * based on size of SDRAM chips. */
 		size = (size & 0xffff) << (3 + 3);
-		/* convert module size to be in Mbits */
+			/* convert module size to be in Mbits */
 		size /= spd_num_chips(slot);
 		print_debug_hex16(size);
 		print_debug(" is the chip size\r\n");
 		if (size < 64)
 			ma = 0;
-		else if (size < 256)
+		if (size < 256)
 			ma = 8;
 		else
 			ma = 0xe;
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index 6f5f1beada..5c29534ac3 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -14,7 +14,7 @@ void amd8111_enable(device_t dev)
 	/* See if we are on the behind the amd8111 pci bridge */
 	bus_dev = dev->bus->dev;
 	if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && 
-	    (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) 
+		(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) 
 	{
 		unsigned devfn;
 		devfn = bus_dev->path.u.pci.devfn + (1 << 3);
@@ -33,7 +33,7 @@ void amd8111_enable(device_t dev)
 		return;
 	}
 	if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
-	    (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) 
+		(lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) 
 	{
 		uint32_t id;
 		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/via/vt8231/Config.lb b/src/southbridge/via/vt8231/Config.lb
index 46b4e26129..b0b2ef5abf 100644
--- a/src/southbridge/via/vt8231/Config.lb
+++ b/src/southbridge/via/vt8231/Config.lb
@@ -1,8 +1,2 @@
 config chip.h
-driver vt8231.o
-driver vt8231_lpc.o
-driver vt8231_acpi.o
-driver vt8231_ide.o
-driver vt8231_nic.o
-#driver vt8231_usb.o
-
+object vt8231.o
diff --git a/src/southbridge/via/vt8231/chip.h b/src/southbridge/via/vt8231/chip.h
index fef4e2913b..bc1e445f26 100644
--- a/src/southbridge/via/vt8231/chip.h
+++ b/src/southbridge/via/vt8231/chip.h
@@ -4,10 +4,18 @@
 extern struct chip_operations southbridge_via_vt8231_ops;
 
 struct southbridge_via_vt8231_config {
-	/* enables of Non-PCI devices */
+	/* PCI function enables */
+	/* i.e. so that pci scan bus will find them. */
+	/* I am putting in IDE as an example but obviously this needs
+	 * to be more complete!
+	 */
+	int enable_ide;
+	/* enables of functions of devices */
+	int enable_usb;
 	int enable_native_ide;
 	int enable_com_ports;
 	int enable_keyboard;
+	int enable_nvram;
 };
 
 #endif /* _SOUTHBRIDGE_VIA_VT8231 */
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c
index 514d0c0626..d78bb2cf86 100644
--- a/src/southbridge/via/vt8231/vt8231.c
+++ b/src/southbridge/via/vt8231/vt8231.c
@@ -1,73 +1,441 @@
-#include <console/console.h>
+
+#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
-
-#include <pc80/mc146818rtc.h>
-#include <pc80/keyboard.h>
-
+#include <console/console.h>
 #include "vt8231.h"
 #include "chip.h"
 
-/* Base 8231 controller */
-static device_t lpc_dev;
+void pc_keyboard_init(void);
 
-void hard_reset(void)
+void hard_reset(void) 
 {
-        printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
+	printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
+}
+
+static void usb_on(int enable)
+{
+	unsigned char regval;
+
+	/* Base 8231 controller */
+	device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
+	/* USB controller 1 */
+	device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
+	/* USB controller 2 */
+	device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
+	
+	/* enable USB1 */
+	if(dev2) {
+		if (enable) {
+			pci_write_config8(dev2, 0x3c, 0x05);
+			pci_write_config8(dev2, 0x04, 0x07);
+		} else {
+			pci_write_config8(dev2, 0x3c, 0x00);
+			pci_write_config8(dev2, 0x04, 0x00);
+		}
+	}
+	
+	if(dev0) {
+		regval = pci_read_config8(dev0, 0x50);
+		if (enable) 
+			regval &= ~(0x10);    
+		else
+			regval |= 0x10;    	      
+		pci_write_config8(dev0, 0x50, regval);
+	}
+	
+	/* enable USB2 */
+	if(dev3) {
+		if (enable) {
+			pci_write_config8(dev3, 0x3c, 0x05);
+			pci_write_config8(dev3, 0x04, 0x07);
+		} else {
+			pci_write_config8(dev3, 0x3c, 0x00);
+			pci_write_config8(dev3, 0x04, 0x00);
+		}
+	}
+	
+	if(dev0) {
+		regval = pci_read_config8(dev0, 0x50);
+		if (enable) 
+			regval &= ~(0x20);    
+		else
+			regval |= 0x20;    
+		pci_write_config8(dev0, 0x50, regval);
+	}
 }
 
 static void keyboard_on(void)
 {
 	unsigned char regval;
+	
+	/* Base 8231 controller */
+	device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
+	
+	/* kevinh/Ispiri - update entire function to use 
+	   new pci_write_config8 */
 
-	if (lpc_dev) {
-		regval = pci_read_config8(lpc_dev, 0x51);
+	if (dev0) {
+		regval = pci_read_config8(dev0, 0x51);
 		regval |= 0x0f; 
-		pci_write_config8(lpc_dev, 0x51, regval);
+		pci_write_config8(dev0, 0x51, regval);
 	}
 	init_pc_keyboard(0x60, 0x64, 0);
 }
 
-static void com_port_on(void)
+static void nvram_on(void)
 {
-#if 0
-	// enable com1 and com2. 
-	enables = pci_read_config8(dev, 0x6e);
-	
-	/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
-	 * is enable com port a as com1 kevinh/Ispiri - Old code
-	 * thought 0x01 would make it com1, that was wrong enables =
-	 * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e,
-	 * enables); // note: this is also a redo of some port of
-	 * assembly, but we want everything up.
+	/*
+	 * the VIA 8231 South has a very different nvram setup than the 
+	 * piix4e ...
+	 * turn on ProMedia nvram.
+	 * TO DO: use the PciWriteByte function here.
 	 */
-
-	/* set com1 to 115 kbaud not clear how to do this yet.
-	 * forget it; done in assembly.
+	
+	/*
+	 * kevinh/Ispiri - I don't think this is the correct address/value
+	 * intel_conf_writeb(0x80008841, 0xFF);
 	 */
-#endif
 }
 
-/* FixME: to be removed ? */
-static void vt8231_enable(struct device *dev)
+
+/*
+ * Enable the ethernet device and turn off stepping (because it is integrated 
+ * inside the southbridge)
+ */
+static void ethernet_fixup()
+{
+	device_t	edev;
+	uint8_t		byte;
+
+	printk_info("Ethernet fixup\n");
+
+	edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
+	if (edev) {
+		printk_debug("Configuring VIA LAN\n");
+		
+		/* We don't need stepping - though the device supports it */
+		byte = pci_read_config8(edev, PCI_COMMAND);
+		byte &= ~PCI_COMMAND_WAIT;
+		pci_write_config8(edev, PCI_COMMAND, byte);
+	} else {
+		printk_debug("VIA LAN not found\n");
+	}
+}
+
+
+/* we need to do things in this function so that PCI scan will find 
+ * them.  One problem here is that we can't use ANY of the new device 
+ * stuff. This work here precedes all that.      
+ * Fundamental problem with linuxbios V2 architecture.
+ * You can't do pci control in the C code without having done a PCI scan.
+ * But in some cases you need to to pci control in the c code before doing
+ * a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
+ * that has functions with the same name but different type signatures
+ * (e.g. device_t). This needs to get fixed. We need low-level pci scans
+ * in the C code. 
+ */
+static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) 
+{
+	/*
+	  unsigned long busdevfn = 0x8000;
+	  if (conf->enable_ide) {
+	  printk_debug("%s: enabling IDE function\n", __FUNCTION__);
+	  }
+	*/
+}
+
+/* PIRQ init
+ */
+void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
+
+
+static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
+static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
+static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
+
+/*
+	Our IDSEL mappings are as follows
+	PCI slot is AD31          (device 15) (00:14.0)
+	Southbridge is AD28       (device 12) (00:11.0)
+*/
+static void pci_routing_fixup(struct device *dev)
+{
+
+	printk_info("%s: dev is %p\n", __FUNCTION__, dev);
+	if (dev) {
+		/* initialize PCI interupts - these assignments depend
+		   on the PCB routing of PINTA-D 
+
+		   PINTA = IRQ11
+		   PINTB = IRQ5
+		   PINTC = IRQ10
+		   PINTD = IRQ12
+		*/
+		pci_write_config8(dev, 0x55, 0xb0);
+		pci_write_config8(dev, 0x56, 0xa5);
+		pci_write_config8(dev, 0x57, 0xc0);
+	}
+
+	// Standard southbridge components
+	printk_info("setting southbridge\n");
+	pci_assign_irqs(0, 0x11, southbridgeIrqs);
+
+	// Ethernet built into southbridge
+	printk_info("setting ethernet\n");
+	pci_assign_irqs(0, 0x12, enetIrqs);
+
+	// PCI slot
+	printk_info("setting pci slot\n");
+	pci_assign_irqs(0, 0x14, slotIrqs);
+	printk_info("%s: DONE\n", __FUNCTION__);
+}
+
+
+void
+dump_south(void)
+{
+	device_t dev0;
+	dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
+	int i,j;
+	
+	for(i = 0; i < 256; i += 16) {
+		printk_debug("0x%x: ", i);
+		for(j = 0; j < 16; j++) {
+			printk_debug("%02x ", pci_read_config8(dev0, i+j));
+		}
+		printk_debug("\n");
+	}
+}
+
+static void vt8231_init(struct southbridge_via_vt8231_config *conf)
 {
-	struct southbridge_via_vt8231_config *conf = dev->chip_info;
-
-	if (!lpc_dev) {
-		/* the first time called, enable devices not on PCI bus
-		 * FIXME: is that device struct there yet? */
-		lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
-					  PCI_DEVICE_ID_VIA_8231, 0);
-		if (conf->enable_keyboard)
-			keyboard_on();
-		if (conf->enable_com_ports)
-			com_port_on();
+	unsigned char enables;
+	device_t dev0;
+	device_t dev1;
+	device_t devpwr;
+	
+	// to do: use the pcibios_find function here, instead of 
+	// hard coding the devfn. 
+	// done - kevinh/Ispiri
+	printk_debug("vt8231 init\n");
+	/* Base 8231 controller */
+	dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
+	/* IDE controller */
+	dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
+	/* Power management controller */
+	devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
+
+	// enable the internal I/O decode
+	enables = pci_read_config8(dev0, 0x6C);
+	enables |= 0x80;
+	pci_write_config8(dev0, 0x6C, enables);
+	
+	// Map 4MB of FLASH into the address space
+	pci_write_config8(dev0, 0x41, 0x7f);
+	
+	// Set bit 6 of 0x40, because Award does it (IO recovery time)
+	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
+	// interrupts can be properly marked as level triggered.
+	enables = pci_read_config8(dev0, 0x40);
+	pci_write_config8(dev0, 0x40, enables);
+	
+	// Set 0x42 to 0xf0 to match Award bios
+	enables = pci_read_config8(dev0, 0x42);
+	enables |= 0xf0;
+	pci_write_config8(dev0, 0x42, enables);
+	
+	// Set bit 3 of 0x4a, to match award (dummy pci request)
+	enables = pci_read_config8(dev0, 0x4a);
+	enables |= 0x08;
+	pci_write_config8(dev0, 0x4a, enables);
+	
+	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
+	enables = pci_read_config8(dev0, 0x4f);
+	enables |= 0x08;
+	pci_write_config8(dev0, 0x4f, enables);
+	
+	// Set 0x58 to 0x03 to match Award
+	pci_write_config8(dev0, 0x58, 0x03);
+	
+	// enable the ethernet/RTC
+	if(dev0) {
+		enables = pci_read_config8(dev0, 0x51);
+		enables |= 0x18; 
+		pci_write_config8(dev0, 0x51, enables);
 	}
+	
+	
+	// enable com1 and com2. 
+	if (conf->enable_com_ports) {
+		enables = pci_read_config8(dev0, 0x6e);
+		
+		/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
+		 * is enable com port a as com1 kevinh/Ispiri - Old code
+		 * thought 0x01 would make it com1, that was wrong enables =
+		 * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
+		 * enables); // note: this is also a redo of some port of
+		 * assembly, but we want everything up.
+		 */
+		
+		/* set com1 to 115 kbaud not clear how to do this yet.
+		 * forget it; done in assembly.
+		 */
+
+	}
+	// enable IDE, since Linux won't do it.
+	// First do some more things to devfn (17,0)
+	// note: this should already be cleared, according to the book. 
+	enables = pci_read_config8(dev0, 0x50);
+	printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
+	enables &= ~8; // need manifest constant here!
+	printk_debug("set IDE reg. 50 to 0x%x\n", enables);
+	pci_write_config8(dev0, 0x50, enables);
+	
+	// set default interrupt values (IDE)
+	enables = pci_read_config8(dev0, 0x4c);
+	printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
+	// clear out whatever was there. 
+	enables &= ~0xf;
+	enables |= 4;
+	printk_debug("setting reg. 4c to 0x%x\n", enables);
+	pci_write_config8(dev0, 0x4c, enables);
+	
+	// set up the serial port interrupts. 
+	// com2 to 3, com1 to 4
+	pci_write_config8(dev0, 0x46, 0x04);
+	pci_write_config8(dev0, 0x47, 0x03);
+	pci_write_config8(dev0, 0x6e, 0x98);
+	//
+	// Power management setup
+	//
+	// Set ACPI base address to IO 0x4000
+	pci_write_config32(devpwr, 0x48, 0x4001);
+	
+	// Enable ACPI access (and setup like award)
+	pci_write_config8(devpwr, 0x41, 0x84);
+	
+	// Set hardware monitor base address to IO 0x6000
+	pci_write_config32(devpwr, 0x70, 0x6001);
+	
+	// Enable hardware monitor (and setup like award)
+	pci_write_config8(devpwr, 0x74, 0x01);
+	
+	// set IO base address to 0x5000
+	pci_write_config32(devpwr, 0x90, 0x5001);
+	
+	// Enable SMBus 
+	pci_write_config8(devpwr, 0xd2, 0x01);
+	
+	//
+	// IDE setup
+	//
+	if (! conf->enable_native_ide) {
+		// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
+		// interrupts.  Using PCI ints confuses linux for some reason.
+		
+		printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
+		enables = pci_read_config8(dev1, 0x42);
+		printk_debug("enables in reg 0x42 0x%x\n", enables);
+		enables &= ~0xc0;		// compatability mode
+		pci_write_config8(dev1, 0x42, enables);
+		enables = pci_read_config8(dev1, 0x42);
+		printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
+	}
+	
+	enables = pci_read_config8(dev1, 0x40);
+	printk_debug("enables in reg 0x40 0x%x\n", enables);
+	enables |= 3;
+	pci_write_config8(dev1, 0x40, enables);
+	enables = pci_read_config8(dev1, 0x40);
+	printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+	
+	// Enable prefetch buffers
+	enables = pci_read_config8(dev1, 0x41);
+	enables |= 0xf0;
+	pci_write_config8(dev1, 0x41, enables);
+	
+	// Lower thresholds (cause award does it)
+	enables = pci_read_config8(dev1, 0x43);
+	enables &= ~0x0f;
+	enables |=  0x05;
+	pci_write_config8(dev1, 0x43, enables);
+	
+	// PIO read prefetch counter (cause award does it)
+	pci_write_config8(dev1, 0x44, 0x18);
+	
+	// Use memory read multiple
+	pci_write_config8(dev1, 0x45, 0x1c);
+	
+	// address decoding. 
+	// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
+	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
+	// used in native mode - I've changed back to classic
+	enables = pci_read_config8(dev1, 0x9);
+	printk_debug("enables in reg 0x9 0x%x\n", enables);
+	// by the book, set the low-order nibble to 0xa. 
+	if (conf->enable_native_ide) {
+		enables &= ~0xf;
+		// cf/cg silicon needs an 'f' here. 
+		enables |= 0xf;
+	} else {
+		enables &= ~0x5;
+	}
+	
+	pci_write_config8(dev1, 0x9, enables);
+	enables = pci_read_config8(dev1, 0x9);
+	printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+	
+	// standard bios sets master bit. 
+	enables = pci_read_config8(dev1, 0x4);
+	printk_debug("command in reg 0x4 0x%x\n", enables);
+	enables |= 7;
+	
+	// No need for stepping - kevinh@ispiri.com
+	enables &= ~0x80;
+	
+	pci_write_config8(dev1, 0x4, enables);
+	enables = pci_read_config8(dev1, 0x4);
+	printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+	
+	if (! conf->enable_native_ide) {
+		// Use compatability mode - per award bios
+		pci_write_config32(dev1, 0x10, 0x0);
+		pci_write_config32(dev1, 0x14, 0x0);
+		pci_write_config32(dev1, 0x18, 0x0);
+		pci_write_config32(dev1, 0x1c, 0x0);
+		
+		// Force interrupts to use compat mode - just like Award bios
+		pci_write_config8(dev1, 0x3d, 00);
+		pci_write_config8(dev1, 0x3c, 0xff);
+	}
+	
+	
+	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+	pci_write_config8(dev0, 0x40, 0x54);
+	ethernet_fixup();
+	
+	// Start the rtc
+	rtc_init(0);
+}
+
+static void southbridge_init(struct device *dev) {
+	vt8231_init(dev->chip_info);
+	pci_routing_fixup(dev);
+}
+
+struct device_operations vt8231_dev_ops = {
+	.init = &southbridge_init,
+};
+
+static void southbridge_enable(struct device *dev)
+{
+	dev->ops = &vt8231_dev_ops;	
 }
 
 struct chip_operations southbridge_via_vt8231_ops = {
 	CHIP_NAME("VIA vt8231")
-	.enable_dev	= vt8231_enable,
+	.enable_dev	= southbridge_enable,
 };
diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c
deleted file mode 100644
index 40f47b8367..0000000000
--- a/src/southbridge/via/vt8231/vt8231_acpi.c
+++ /dev/null
@@ -1,44 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "vt8231.h"
-
-static void acpi_init(struct device *dev)
-{
-	printk_debug("Configuring VIA ACPI\n");
-
-	// Set ACPI base address to IO 0x4000
-	pci_write_config32(dev, 0x48, 0x4001);
-	
-	// Enable ACPI access (and setup like award)
-	pci_write_config8(dev, 0x41, 0x84);
-	
-	// Set hardware monitor base address to IO 0x6000
-	pci_write_config32(dev, 0x70, 0x6001);
-	
-	// Enable hardware monitor (and setup like award)
-	pci_write_config8(dev, 0x74, 0x01);
-	
-	// set IO base address to 0x5000
-	pci_write_config32(dev, 0x90, 0x5001);
-	
-	// Enable SMBus 
-	pci_write_config8(dev, 0xd2, 0x01);
-}
-
-static struct device_operations acpi_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init		  = acpi_init,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &acpi_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_8231_4,
-};
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index dbb6e213ae..056c4b5b11 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -12,12 +12,12 @@
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf
+#define SMBUS_PIN_CTL  0xf 
 
 /* Define register settings */
 #define HOST_RESET 0xff
-#define DIMM_BASE 0xa0		// 1010000 is base for DIMM in SMBus
-#define READ_CMD  0x01		// 1 in the 0 bit of SMBHSTADD states to READ
+#define DIMM_BASE 0xa0        // 1010000 is base for DIMM in SMBus
+#define READ_CMD  0x01        // 1 in the 0 bit of SMBHSTADD states to READ
 
 
 #define SMBUS_TIMEOUT (100*1000*10)
@@ -27,28 +27,29 @@ static void enable_smbus(void)
 	device_t dev;
 	unsigned char c;
 	/* Power management controller */
-	dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
-
+	dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
+	
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
 	}
+	
 	// set IO base address to SMBUS_IO_BASE
-	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
-
+	pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
+	
 	// Enable SMBus 
 	c = pci_read_config8(dev, 0xd2);
 	c |= 5;
 	pci_write_config8(dev, 0xd2, c);
-
+	
 	/* make it work for I/O ...
 	 */
-	dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
+	dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
 	c = pci_read_config8(dev, 4);
 	c |= 1;
 	pci_write_config8(dev, 4, c);
 	print_debug_hex8(c);
 	print_debug(" is the comm register\r\n");
-
+	
 	print_debug("SMBus controller enabled\r\n");
 }
 
@@ -60,51 +61,52 @@ static inline void smbus_delay(void)
 
 static int smbus_wait_until_active(void)
 {
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1)) {
-			break;
-		}
-	} while (--loops);
-	return loops ? 0 : -4;
+        unsigned long loops;
+        loops = SMBUS_TIMEOUT;
+        do {
+                unsigned char val;
+                smbus_delay();
+                val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+                if ((val & 1)) {
+                        break;
+                }
+        } while(--loops);
+        return loops?0:-4;
 }
 
 static int smbus_wait_until_ready(void)
 {
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1) == 0) {
-			break;
-		}
-		if (loops == (SMBUS_TIMEOUT / 2)) {
-			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-		}
-	} while (--loops);
-	return loops ? 0 : -2;
+        unsigned long loops;
+        loops = SMBUS_TIMEOUT;
+        do {
+                unsigned char val;
+                smbus_delay();
+                val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+                if ((val & 1) == 0) {
+                        break;
+                }
+                if(loops == (SMBUS_TIMEOUT / 2)) {
+                        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+                                SMBUS_IO_BASE + SMBHSTSTAT);
+                }
+        } while(--loops);
+        return loops?0:-2;
 }
 
 static int smbus_wait_until_done(void)
 {
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1) == 0) {
-			break;
-		}
-	} while (--loops);
-	return loops ? 0 : -3;
+        unsigned long loops;
+        loops = SMBUS_TIMEOUT;
+        do {
+                unsigned char val;
+                smbus_delay();
+
+                val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+                if ( (val & 1) == 0) {
+                        break;
+                }
+        } while(--loops);
+        return loops?0:-3;
 }
 
 void smbus_reset(void)
@@ -113,13 +115,13 @@ void smbus_reset(void)
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
-
+	
 	smbus_wait_until_ready();
 	print_debug("After reset status ");
-	print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
+	print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
 	print_debug("\r\n");
 }
-
+  
 static void smbus_print_error(unsigned char host_status_register)
 {
 
@@ -150,95 +152,96 @@ static void smbus_print_error(unsigned char host_status_register)
  */
 static int smbus_read_byte(unsigned device, unsigned address)
 {
-	unsigned char global_control_register;
-	unsigned char global_status_register;
-	unsigned char byte;
-
-	if (smbus_wait_until_ready() < 0) {
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-		if (smbus_wait_until_ready() < 0) {
-			return -2;
-		}
-	}
-
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
-	/* set the command/address... */
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* clear the data byte... */
-	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* start a byte read, with interrupts disabled */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
-	/* poll for it to start */
-	if (smbus_wait_until_active() < 0) {
-		return -4;
-	}
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done() < 0) {
-		return -3;
-	}
+        unsigned char global_control_register;
+        unsigned char global_status_register;
+        unsigned char byte;
+
+        if (smbus_wait_until_ready() < 0) {
+          outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+          if ( smbus_wait_until_ready() < 0 ) {
+              return -2;
+          }
+        }
+
+        /* setup transaction */
+        /* disable interrupts */
+        outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
+        /* set the command/address... */
+        outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+        /* set up for a byte data read */
+        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
+
+        /* clear any lingering errors, so the transaction will run */
+        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+        /* clear the data byte...*/
+        outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+
+        /* start a byte read, with interrupts disabled */
+        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+        /* poll for it to start */
+        if (smbus_wait_until_active() < 0) {
+                return -4;
+        }
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done() < 0) {
+                return -3;
+        }
 
 	/* Ignore the Host Busy & Command Complete ? */
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0));
+        global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1<<1)|(1<<0));
 
-	/* read results of transaction */
-	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+        /* read results of transaction */
+        byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
 
-	if (global_status_register != 0) {
-		return -1;
-	}
-	return byte;
+        if (global_status_register != 0) {
+                return -1;
+        }
+        return byte;
 }
 
 #if 0
 /* SMBus routines borrowed from VIA's Trident Driver */
 /* this works, so I am not going to touch it for now -- rgm */
-static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
+static unsigned char smbus_read_byte(unsigned char devAdr, 
+				unsigned char bIndex) 
 {
 	unsigned int i;
-	unsigned char bData;
-	unsigned char sts = 0;
-
+	unsigned char  bData;
+	unsigned char  sts = 0;
+	
 	/* clear host status */
 	outb(0xff, SMBUS_IO_BASE);
-
+	
 	/* check SMBUS ready */
-	for (i = 0; i < SMBUS_TIMEOUT; i++)
-		if ((inb(SMBUS_IO_BASE) & 0x01) == 0)
+	for ( i = 0; i < SMBUS_TIMEOUT; i++ )
+		if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
 			break;
 
 	/* set host command */
-	outb(bIndex, SMBUS_IO_BASE + 3);
-
+	outb(bIndex, SMBUS_IO_BASE+3);
+	
 	/* set slave address */
-	outb(devAdr | 0x01, SMBUS_IO_BASE + 4);
-
+	outb(devAdr | 0x01, SMBUS_IO_BASE+4);
+	
 	/* start */
-	outb(0x48, SMBUS_IO_BASE + 2);
-
+	outb(0x48, SMBUS_IO_BASE+2);
+	
 	/* SMBUS Wait Ready */
-	for (i = 0; i < SMBUS_TIMEOUT; i++)
-		if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0)
+	for ( i = 0; i < SMBUS_TIMEOUT; i++ )
+		if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
 			break;
 	if ((sts & ~3) != 0) {
 		smbus_print_error(sts);
 		return 0;
 	}
-	bData = inb(SMBUS_IO_BASE + 5);
-
+	bData=inb(SMBUS_IO_BASE+5);
+	
 	return bData;
-
+	
 }
 #endif
 /* for reference, here is the fancier version which we will use at some 
@@ -249,11 +252,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 {
 	unsigned char host_status_register;
 	unsigned char byte;
-
+	
 	reset();
-
+	
 	smbus_wait_until_ready();
-
+	
 	/* setup transaction */
 	/* disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
@@ -262,32 +265,35 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
-
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
+		SMBUS_IO_BASE + SMBHSTCTL);
+	
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* clear the data byte... */
+	
+	/* clear the data byte...*/
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
+	
 	/* start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
-
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+		SMBUS_IO_BASE + SMBHSTCTL);
+	
 	/* poll for transaction completion */
 	smbus_wait_until_done();
-
+	
 	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-
+	
 	/* Ignore the In Use Status... */
 	host_status_register &= ~(1 << 6);
-
+	
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
 	smbus_print_error(byte);
-
+	
 	*result = byte;
 	return host_status_register != 0x02;
 }
 
 
 #endif
+
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
deleted file mode 100644
index 70f256990c..0000000000
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ /dev/null
@@ -1,108 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "vt8231.h"
-#include "chip.h"
-
-static void ide_init(struct device *dev)
-{
-	struct southbridge_via_vt8231_config *conf;
-	unsigned char enables;
-
-	if (!conf->enable_native_ide) {
-		// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
-		// interrupts.  Using PCI ints confuses linux for some reason.
-		
-		printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
-		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 0x%x\n", enables);
-		enables &= ~0xc0;		// compatability mode
-		pci_write_config8(dev, 0x42, enables);
-		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
-	}
-	
-	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 0x%x\n", enables);
-	enables |= 3;
-	pci_write_config8(dev, 0x40, enables);
-	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
-	
-	// Enable prefetch buffers
-	enables = pci_read_config8(dev, 0x41);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x41, enables);
-	
-	// Lower thresholds (cause award does it)
-	enables = pci_read_config8(dev, 0x43);
-	enables &= ~0x0f;
-	enables |=  0x05;
-	pci_write_config8(dev, 0x43, enables);
-	
-	// PIO read prefetch counter (cause award does it)
-	pci_write_config8(dev, 0x44, 0x18);
-	
-	// Use memory read multiple
-	pci_write_config8(dev, 0x45, 0x1c);
-	
-	// address decoding. 
-	// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
-	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
-	// used in native mode - I've changed back to classic
-	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 0x%x\n", enables);
-	// by the book, set the low-order nibble to 0xa. 
-	if (conf->enable_native_ide) {
-		enables &= ~0xf;
-		// cf/cg silicon needs an 'f' here. 
-		enables |= 0xf;
-	} else {
-		enables &= ~0x5;
-	}
-	
-	pci_write_config8(dev, 0x9, enables);
-	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
-	
-	// standard bios sets master bit. 
-	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 0x%x\n", enables);
-	enables |= 7;
-	
-	// No need for stepping - kevinh@ispiri.com
-	enables &= ~0x80;
-	
-	pci_write_config8(dev, 0x4, enables);
-	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
-	
-	if (!conf->enable_native_ide) {
-		// Use compatability mode - per award bios
-		pci_write_config32(dev, 0x10, 0x0);
-		pci_write_config32(dev, 0x14, 0x0);
-		pci_write_config32(dev, 0x18, 0x0);
-		pci_write_config32(dev, 0x1c, 0x0);
-		
-		// Force interrupts to use compat mode - just like Award bios
-		pci_write_config8(dev, 0x3d, 00);
-		pci_write_config8(dev, 0x3c, 0xff);
-	}	
-}
-
-static struct device_operations ide_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init		  = ide_init,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &ide_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_82C586_1,
-};
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
deleted file mode 100644
index 9564b55ae7..0000000000
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ /dev/null
@@ -1,154 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-
-#include <pc80/mc146818rtc.h>
-
-#include "vt8231.h"
-#include "chip.h"
-
-/* PIRQ init
- */
-void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
-static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
-static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
-static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
-
-/*
-	Our IDSEL mappings are as follows
-	PCI slot is AD31          (device 15) (00:14.0)
-	Southbridge is AD28       (device 12) (00:11.0)
-*/
-static void pci_routing_fixup(struct device *dev)
-{
-
-	printk_info("%s: dev is %p\n", __FUNCTION__, dev);
-	if (dev) {
-		/* initialize PCI interupts - these assignments depend
-		   on the PCB routing of PINTA-D 
-
-		   PINTA = IRQ11
-		   PINTB = IRQ5
-		   PINTC = IRQ10
-		   PINTD = IRQ12
-		*/
-		pci_write_config8(dev, 0x55, 0xb0);
-		pci_write_config8(dev, 0x56, 0xa5);
-		pci_write_config8(dev, 0x57, 0xc0);
-	}
-
-	// Standard southbridge components
-	printk_info("setting southbridge\n");
-	pci_assign_irqs(0, 0x11, southbridgeIrqs);
-
-	// Ethernet built into southbridge
-	printk_info("setting ethernet\n");
-	pci_assign_irqs(0, 0x12, enetIrqs);
-
-	// PCI slot
-	printk_info("setting pci slot\n");
-	pci_assign_irqs(0, 0x14, slotIrqs);
-	printk_info("%s: DONE\n", __FUNCTION__);
-}
-
-static void vt8231_init(struct device *dev)
-{
-	unsigned char enables;
-	struct southbridge_via_vt8231_config *conf = dev->chip_info;
-
-	printk_debug("vt8231 init\n");
-
-	// enable the internal I/O decode
-	enables = pci_read_config8(dev, 0x6C);
-	enables |= 0x80;
-	pci_write_config8(dev, 0x6C, enables);
-	
-	// Map 4MB of FLASH into the address space
-	pci_write_config8(dev, 0x41, 0x7f);
-	
-	// Set bit 6 of 0x40, because Award does it (IO recovery time)
-	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
-	// interrupts can be properly marked as level triggered.
-	enables = pci_read_config8(dev, 0x40);
-	pci_write_config8(dev, 0x40, enables);
-	
-	// Set 0x42 to 0xf0 to match Award bios
-	enables = pci_read_config8(dev, 0x42);
-	enables |= 0xf0;
-	pci_write_config8(dev, 0x42, enables);
-	
-	// Set bit 3 of 0x4a, to match award (dummy pci request)
-	enables = pci_read_config8(dev, 0x4a);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4a, enables);
-	
-	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
-	enables = pci_read_config8(dev, 0x4f);
-	enables |= 0x08;
-	pci_write_config8(dev, 0x4f, enables);
-	
-	// Set 0x58 to 0x03 to match Award
-	pci_write_config8(dev, 0x58, 0x03);
-	
-	// enable the ethernet/RTC
-	if (dev) {
-		enables = pci_read_config8(dev, 0x51);
-		enables |= 0x18; 
-		pci_write_config8(dev, 0x51, enables);
-	}
-
-	// enable IDE, since Linux won't do it.
-	// First do some more things to devfn (17,0)
-	// note: this should already be cleared, according to the book. 
-	enables = pci_read_config8(dev, 0x50);
-	printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
-	enables &= ~8; // need manifest constant here!
-	printk_debug("set IDE reg. 50 to 0x%x\n", enables);
-	pci_write_config8(dev, 0x50, enables);
-	
-	// set default interrupt values (IDE)
-	enables = pci_read_config8(dev, 0x4c);
-	printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
-	// clear out whatever was there. 
-	enables &= ~0xf;
-	enables |= 4;
-	printk_debug("setting reg. 4c to 0x%x\n", enables);
-	pci_write_config8(dev, 0x4c, enables);
-	
-	// set up the serial port interrupts. 
-	// com2 to 3, com1 to 4
-	pci_write_config8(dev, 0x46, 0x04);
-	pci_write_config8(dev, 0x47, 0x03);
-	pci_write_config8(dev, 0x6e, 0x98);
-
-	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
-	pci_write_config8(dev, 0x40, 0x54);
-	//ethernet_fixup();
-	
-	// Start the rtc
-	rtc_init(0);
-}
-
-static void southbridge_init(struct device *dev)
-{
-	vt8231_init(dev);
-	pci_routing_fixup(dev);
-}
-
-static struct device_operations vt8231_lpc_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init		  = &southbridge_init,
-	.scan_bus	  = scan_static_bus,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static struct pci_driver lpc_driver __pci_driver = {
-	.ops	= &vt8231_lpc_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_8231,
-};
diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c
deleted file mode 100644
index 13da26345c..0000000000
--- a/src/southbridge/via/vt8231/vt8231_nic.c
+++ /dev/null
@@ -1,37 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "vt8231.h"
-
-/*
- * Enable the ethernet device and turn off stepping (because it is integrated 
- * inside the southbridge)
- */
-static void nic_init(struct device *dev)
-{
-	uint8_t		byte;
-
-	printk_debug("Configuring VIA LAN\n");
-
-	/* We don't need stepping - though the device supports it */
-	byte = pci_read_config8(dev, PCI_COMMAND);
-	byte &= ~PCI_COMMAND_WAIT;
-	pci_write_config8(dev, PCI_COMMAND, byte);
-}
-
-static struct device_operations nic_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init		  = nic_init,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &nic_ops,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_8233_7,
-};
diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c
deleted file mode 100644
index 3dd0b4272b..0000000000
--- a/src/southbridge/via/vt8231/vt8231_usb.c
+++ /dev/null
@@ -1,52 +0,0 @@
-
-static void usb_on(int enable)
-{
-	unsigned char regval;
-
-	/* Base 8231 controller */
-	device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
-	/* USB controller 1 */
-	device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
-	/* USB controller 2 */
-	device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
-	
-	/* enable USB1 */
-	if(dev2) {
-		if (enable) {
-			pci_write_config8(dev2, 0x3c, 0x05);
-			pci_write_config8(dev2, 0x04, 0x07);
-		} else {
-			pci_write_config8(dev2, 0x3c, 0x00);
-			pci_write_config8(dev2, 0x04, 0x00);
-		}
-	}
-	
-	if(dev0) {
-		regval = pci_read_config8(dev0, 0x50);
-		if (enable) 
-			regval &= ~(0x10);    
-		else
-			regval |= 0x10;    	      
-		pci_write_config8(dev0, 0x50, regval);
-	}
-	
-	/* enable USB2 */
-	if(dev3) {
-		if (enable) {
-			pci_write_config8(dev3, 0x3c, 0x05);
-			pci_write_config8(dev3, 0x04, 0x07);
-		} else {
-			pci_write_config8(dev3, 0x3c, 0x00);
-			pci_write_config8(dev3, 0x04, 0x00);
-		}
-	}
-	
-	if(dev0) {
-		regval = pci_read_config8(dev0, 0x50);
-		if (enable) 
-			regval &= ~(0x20);    
-		else
-			regval |= 0x20;    
-		pci_write_config8(dev0, 0x50, regval);
-	}
-}
diff --git a/targets/arima/hdama/Config.lb b/targets/arima/hdama/Config.lb
index 1dce4fdc8b..8e5a16c02e 100644
--- a/targets/arima/hdama/Config.lb
+++ b/targets/arima/hdama/Config.lb
@@ -6,22 +6,20 @@
 target hdama
 mainboard arima/hdama
 
-option ROM_SIZE=487424
-
 # Arima hdama
 romimage "normal"
 	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x16000
+	option ROM_IMAGE_SIZE=0x10400
 	option LINUXBIOS_EXTRA_VERSION=".0Normal"
-	payload /home/ollie/work/filo-0.4.1/filo.elf
-#	payload /etc/hosts
+	payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
 end
 
 romimage "fallback" 
 	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x16000
+	option ROM_IMAGE_SIZE=0x10400
 	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
-	payload /home/ollie/work/filo-0.4.1/filo.elf
+	payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
+# use this to test a build if you don't have the etherboot
 #	payload /etc/hosts
 end
 
diff --git a/targets/ibm/e325/Config.lb b/targets/ibm/e325/Config.lb
index 709c1d853a..0a9d6a02c2 100644
--- a/targets/ibm/e325/Config.lb
+++ b/targets/ibm/e325/Config.lb
@@ -1,9 +1,87 @@
 # the IBM E325
 # This will make a target directory of ./e325
 
+loadoptions
+
 target e325
 
-mainboard ibm/e325
+uses ARCH
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_SERIAL_POST
+uses NO_POST
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
+uses FALLBACK_SIZE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
+uses i586
+uses i686
+uses INTEL_PPRO_MTRR
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses k7
+uses k8
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses STACK_SIZE
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses HAVE_OPTION_TABLE
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses  DEFAULT_CONSOLE_LOGLEVEL
+uses  CONFIG_CONSOLE_SERIAL8250
+uses MAINBOARD
+uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
+
+option CONFIG_CHIP_CONFIGURE=1
+
+option  MAXIMUM_CONSOLE_LOGLEVEL=9
+option  DEFAULT_CONSOLE_LOGLEVEL=9
+option  CONFIG_CONSOLE_SERIAL8250=1
+option  CONFIG_SERIAL_POST=1
+option  NO_POST=0
+
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option i586=1
+option INTEL_PPRO_MTRR=1
+option k7=1
+option k8=1
+
+option ROM_SIZE=1048576
+
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=131072
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00004000
 
 #
 ###
@@ -17,16 +95,16 @@ romimage "normal"
 	option USE_FALLBACK_IMAGE=0
 	option ROM_IMAGE_SIZE=0x10000
 	option LINUXBIOS_EXTRA_VERSION=".0Normal"
-#	payload ../../filo.elf
-        payload /home/ollie/work/filo-0.4.1/filo.elf
+	mainboard ibm/e325
+	payload ../../filo.elf
 end
 
 romimage "fallback" 
 	option USE_FALLBACK_IMAGE=1
 	option ROM_IMAGE_SIZE=0x10000
 	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
-#	payload ../../filo.elf
-        payload /home/ollie/work/filo-0.4.1/filo.elf
+	mainboard ibm/e325
+	payload ../../filo.elf
 # use this to test a build if you don't have the etherboot
 #	payload /etc/hosts
 end
diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb
index ff484d60ef..ba4297d648 100644
--- a/targets/via/epia/Config.lb
+++ b/targets/via/epia/Config.lb
@@ -3,12 +3,6 @@
 
 target epia
 mainboard via/epia
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=9
-
 #
 # Via Epia
 romimage "normal"
@@ -17,9 +11,7 @@ romimage "normal"
 	option LINUXBIOS_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-        payload /home/ollie/work/filo-0.4.1/filo.elf
-
+	payload ../../../../../lnxieepro100.ebi
 end
 
 romimage "fallback" 
@@ -28,8 +20,7 @@ romimage "fallback"
 	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
-#	payload ../../../../../lnxieepro100.ebi
-        payload /home/ollie/work/filo-0.4.1/filo.elf
+	payload ../../../../../lnxieepro100.ebi
 end
 
 buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"