diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-04-02 17:28:46 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2014-10-29 19:20:59 +0100 |
| commit | 1c6d919eb051dd8a42ee7d1758a348984ff08563 (patch) | |
| tree | 5941ec18f2f56f0cfca9e6697e3509f9d22b43f4 | |
| parent | 35170388ed401908532ecb0a3c4ba0e12de99294 (diff) | |
libpayload: usb: ehci: Honor 10ms reset recovery period
This patch adds the 10ms TRSTRCY delay between a reset and the following
Set Address command that is required by the USB 2.0 specification to the
EHCI root hub driver. The generic_hub driver that's used for XHCI and
external hubs already included this delay. This is such a glaring
violation of the spec that I'm really amazed how many USB 2.0 devices
we tested before seemed perfectly fine with responding to a Set Address
within 2 microframes of the reset...
It also increases the port reset hold delay by one millisecond to avoid
an ugly race condition on Tegra SoCs: they decided to time the 50ms
themselves instead of relying on the CPU to do it (fair enough), and to
automatically transition Port Reset to 0 and Port Enable to 1 after that
(bad idea). If the CPU's read-modify-write to clear Port Reset races
exactly with the host controller setting Port Enable, we may end up
clearing the bit again and going into the companion controller handoff
path later on. The added millisecond shouldn't cause any problems for
other host controllers and is not a big deal compared to other delays in
this code path.
BUG=chrome-os-partner:26749
TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a
blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always
gets detected correctly.
Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/189872
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d
Reviewed-on: http://review.coreboot.org/7221
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | payloads/libpayload/drivers/usb/ehci_rh.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5c4daeda8a..67f63cc481 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -98,8 +98,8 @@ ehci_rh_scanport (usbdev_t *dev, int port) */ RH_INST(dev)->ports[port] = (RH_INST(dev)->ports[port] & ~P_PORT_ENABLE) | P_PORT_RESET; - /* Wait a bit while reset is active. */ - mdelay(50); // usb20 spec 7.1.7.5 (TDRSTR) + /* Wait a bit while reset is active (+1 to avoid Tegra race). */ + mdelay(50 + 1); // usb20 spec 7.1.7.5 (TDRSTR) /* Deassert reset. */ RH_INST(dev)->ports[port] &= ~P_PORT_RESET; @@ -113,6 +113,8 @@ ehci_rh_scanport (usbdev_t *dev, int port) return; } + mdelay(10); /* TRSTRCY (USB 2.0 spec 7.1.7.5) */ + /* If the host controller enabled the port, it's a high-speed * device, otherwise it's full-speed. */ |