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authorFelix Held <felix-coreboot@felixheld.de>2023-04-29 02:02:48 +0200
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-05-03 16:15:53 +0000
commit19d1c16c326a274e732526621d07516f6d6ca6db (patch)
tree9c864e2eb0cb11442258dff8cd0489b27d98c7cf
parent026caf5def38df8cc2dca0e1acd7adc063e03951 (diff)
soc/amd/common/block/lpc/lpc: report eSPI MMIO
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/soc/amd/common/block/lpc/lpc.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 5b836eac7b..edc74762b2 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -123,7 +123,10 @@ static void lpc_read_resources(struct device *dev)
/* Add a memory resource for the SPI BAR. */
mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);
- res = new_resource(dev, 3); /* IOAPIC */
+ /* Add a memory resource for the eSPI MMIO */
+ mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
+
+ res = new_resource(dev, 4); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;