summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKane Chen <kane.chen@intel.com>2017-12-27 12:11:23 +0800
committerFurquan Shaikh <furquan@google.com>2018-01-02 07:39:12 +0000
commit14e0fa5ee0fe4bcc47e4249cd9f2be20c4e97b61 (patch)
tree90e25ba93ec5881b23cd160e756d1afa35c2354a
parent8e4384d0b4058e766cd9826774584c3a58f90a4f (diff)
soc/intel/skylake: Add device setting for sata power optimization
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 00088b9aad..4e8cb8155d 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -542,6 +542,9 @@ struct soc_intel_skylake_config {
/* PCH Trip Temperature */
u8 pch_trip_temp;
+
+ /* Enable/Disable Sata power optimization */
+ u8 SataPwrOptEnable;
};
typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 24a239e3b5..ccda3032c5 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -219,6 +219,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
params->SataSpeedLimit = config->SataSpeedLimit;
+ params->SataPwrOptEnable = config->SataPwrOptEnable;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;