diff options
| author | Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com> | 2019-05-08 18:08:08 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-10 15:14:19 +0000 |
| commit | 1360b9a73f5389efd94f0de36588d71f6f8cd1d1 (patch) | |
| tree | 8f08ab47bf9314bca98529ae622ffaf917ef44e5 | |
| parent | bddfa59f1da418b7c144a4b0eee5e0303aa1183c (diff) | |
mb/google/sarien/variants/arcada: Set tcc offset value
Set tcc offset value to 1 degree celsius for Arcada system.
BRANCH=None
BUG=b:122636962
TEST=Built and tested on Arcada system
Signed-off-by: Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com>
Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0cc9970488..27c61f3563 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -161,7 +161,7 @@ chip soc/intel/cannonlake #| I2C4 | H1 TPM | #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |