diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-06-22 22:22:20 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-31 17:34:48 +0000 |
| commit | 0a15ed57c6a0fd71f4d7a1b7d75bb442e3ca3c87 (patch) | |
| tree | 7cbecd6f30ae63c0a6b7398266d9679cbe0dd040 | |
| parent | 8ab105d490093671087d58c9c88fdc51f3a7850c (diff) | |
google/kahlee: Add mainboard GPIOs to ACPI
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/google/kahlee/chromeos.c | 15 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 3 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index f84c618289..4112db5677 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -18,7 +18,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <boot/coreboot_tables.h> #include <console/console.h> +#include <soc/gpio.h> +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_122 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -33,5 +36,15 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - return 0; + return gpio_get(CROS_WP_GPIO); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 9d84f0d56b..48a05a97d7 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -19,6 +19,7 @@ #include <agesawrapper.h> #include <amd_pci_util.h> #include <ec.h> +#include <vendorcode/google/chromeos/chromeos.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -91,6 +92,8 @@ static void kahlee_enable(device_t dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { |