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authorRob Barnes <robbarnes@google.com>2021-07-28 11:33:22 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-09-10 22:58:28 +0000
commit058048c00cd95af4cd6ae34d2d50b087aa038104 (patch)
tree277a02a74f0828cb115eeb9afde0faa84042082e
parentb28a035ea081be668311d70106b843c0204963fa (diff)
mb/google/guybrush: Document USB mapping in devicetree
Add a short documenting comment to each usb entry in devicetree so it is clear which function each usb port maps to. BUG=None TEST=Build BRANCH=None Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 8629a64036..edd0a020b4 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -93,6 +93,7 @@ chip soc/amd/cezanne
register "usb_phy_custom" = "1"
register "usb_phy" = "{
+ /* Left USB C0 Port */
.Usb2PhyPort[0] = {
.compdstune = 3,
.sqrxtune = 3,
@@ -104,6 +105,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 1,
},
+ /* Left USB A0 Port or WWAN */
.Usb2PhyPort[1] = {
.compdstune = 3,
.sqrxtune = 3,
@@ -115,6 +117,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 1,
},
+ /* User facing camera */
.Usb2PhyPort[2] = {
.compdstune = 1,
.sqrxtune = 3,
@@ -126,6 +129,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 2,
},
+ /* World facing camera */
.Usb2PhyPort[3] = {
.compdstune = 1,
.sqrxtune = 3,
@@ -137,6 +141,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 2,
},
+ /* Right USB C1 Port */
.Usb2PhyPort[4] = {
.compdstune = 3,
.sqrxtune = 3,
@@ -148,6 +153,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 1,
},
+ /* Right USB A1 Port */
.Usb2PhyPort[5] = {
.compdstune = 5,
.sqrxtune = 3,
@@ -159,6 +165,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 1,
},
+ /* WiFi / Bluetooth */
.Usb2PhyPort[6] = {
.compdstune = 1,
.sqrxtune = 3,
@@ -170,6 +177,7 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 2,
},
+ /* Smart Card */
.Usb2PhyPort[7] = {
.compdstune = 1,
.sqrxtune = 3,
@@ -181,25 +189,28 @@ chip soc/amd/cezanne
.txhsxvtune = 3,
.txrestune = 2,
},
-
+ /* Left USB C0 Port */
.Usb3PhyPort[0] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
+ /* Left USB A0 Port or WWAN */
.Usb3PhyPort[1] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
+ /* Right USB C1 Port */
.Usb3PhyPort[2] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
+ /* Right USB A1 Port */
.Usb3PhyPort[3] = {
.tx_term_ctrl=2,
.rx_term_ctrl=2,