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authorElyes Haouas <ehaouas@noos.fr>2024-08-14 05:55:33 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-10-23 23:41:58 +0000
commit04f8a662953402ee6c01aae89a1a432fa022d785 (patch)
tree10f13cd37c122c5e7eecffb628096936e73a31d1
parentd4ac047c78c3fec22107bc66a499144ab5602a5f (diff)
device/dram/ddr2: Use boolean for spd_dimm_is_registered_ddr2()
Change-Id: I475f0c7582148e9b9f86b542f753a6654e9f9135 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
-rw-r--r--src/device/dram/ddr2.c6
-rw-r--r--src/include/device/dram/ddr2.h3
2 files changed, 5 insertions, 4 deletions
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index ce7a3bf777..6ac059f259 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -24,13 +24,13 @@
*
* @param type DIMM type. This is byte[20] of the SPD.
*/
-int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
+bool spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
{
if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) ||
(type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
- return 1;
+ return true;
- return 0;
+ return false;
}
/**
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h
index f3605b289d..289ba2f072 100644
--- a/src/include/device/dram/ddr2.h
+++ b/src/include/device/dram/ddr2.h
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <spd.h>
#include <device/dram/common.h>
+#include <stdbool.h>
/** Maximum SPD size supported */
#define SPD_SIZE_MAX_DDR2 128
@@ -154,7 +155,7 @@ struct dimm_attr_ddr2_st {
u32 serial;
};
-int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);
+bool spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);
u8 spd_ddr2_calc_checksum(u8 *spd, int len);
u32 spd_decode_spd_size_ddr2(u8 byte0);
u32 spd_decode_eeprom_size_ddr2(u8 byte1);