diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-09 21:01:38 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-12 05:09:21 +0000 |
| commit | bd72bfece2da38ff60a99a3bbb15bd3243a5d647 (patch) | |
| tree | 3d76eeab389887f45cd2ebf48bb9b8a9ebdda99a | |
| parent | 8e275af3eefa17e60cf028ec862f77c241d10ede (diff) | |
cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
The disablement of SSE2 was not honoured since there is explicit
select under CPU_INTEL_MODEL_F2X. The removed commentary originates
probably from ROMCC romstage implementation.
Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/cpu/intel/socket_mPGA604/Kconfig | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 7b086990f7..12c8e37ab6 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -7,20 +7,12 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X select MMX - select SSE select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE -# mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on -# enabling it, so disable it for now. -config SSE2 - bool - default n - config DCACHE_RAM_BASE hex default 0xfefc0000 |