From bd72bfece2da38ff60a99a3bbb15bd3243a5d647 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 9 Nov 2022 21:01:38 +0200 Subject: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The disablement of SSE2 was not honoured since there is explicit select under CPU_INTEL_MODEL_F2X. The removed commentary originates probably from ROMCC romstage implementation. Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/cpu/intel/socket_mPGA604/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 7b086990f7..12c8e37ab6 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -7,20 +7,12 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X select MMX - select SSE select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE -# mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on -# enabling it, so disable it for now. -config SSE2 - bool - default n - config DCACHE_RAM_BASE hex default 0xfefc0000 -- cgit v1.2.3