diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-06-01 16:01:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:51:10 +0000 |
| commit | 7454005a4fd611cc2ad4b490442834e50272fd1b (patch) | |
| tree | bd51de43378fe6553bd4b640551f65738a3dfc65 | |
| parent | 4a3a73c0425e90a6cffd99d4b06766eff25d171f (diff) | |
soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS
FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 59ccc6f98e..9c6450e73c 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -66,4 +66,6 @@ config FSP_TEMP_RAM_SIZE config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y +select CACHE_MRC_SETTINGS + endif |