From 7454005a4fd611cc2ad4b490442834e50272fd1b Mon Sep 17 00:00:00 2001
From: Jonathan Zhang <jonzhang@fb.com>
Date: Mon, 1 Jun 2020 16:01:08 -0700
Subject: soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS

FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/cpx/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 59ccc6f98e..9c6450e73c 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -66,4 +66,6 @@ config FSP_TEMP_RAM_SIZE
 config SOC_INTEL_COMMON_BLOCK_P2SB
 	def_bool y
 
+select CACHE_MRC_SETTINGS
+
 endif
-- 
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