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authorPatrick Rudolph <siro@das-labor.org>2015-07-12 11:39:45 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-13 01:59:11 +0200
commit073b017bed5e51244f0578056d52e6f88734d64b (patch)
treef0266b8366d99f734e65fb64e1999239ffb2fbda
parent03a88d3773ae1b2cb54cad176231ebf8ab8bc226 (diff)
intel raminit: whitespace fixes
Remove whitespace errors. Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10888 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 3740a02706..02825f8197 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -2370,16 +2370,16 @@ static void adjust_high_timB(ramctr_timing * ctrl)
wait_428c(channel);
FOR_ALL_LANES {
u64 res =
- read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 4);
- res |=
- ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 8)) << 32;
- ctrl->timings[channel][slotrank].lanes[lane].timB +=
- get_timB_high_adjust(res) * 64;
-
- printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res);
- printram("Bval+: %d, %d, %d, %x\n", channel,
+ read32(DEFAULT_MCHBAR + lane_registers[lane] +
+ 0x100 * channel + 4);
+ res |=
+ ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] +
+ 0x100 * channel + 8)) << 32;
+ ctrl->timings[channel][slotrank].lanes[lane].timB +=
+ get_timB_high_adjust(res) * 64;
+
+ printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res);
+ printram("Bval+: %d, %d, %d, %x\n", channel,
slotrank, lane,
ctrl->timings[channel][slotrank].lanes[lane].
timB);