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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 20:21:09 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 15:44:02 +0000 |
| commit | c86acf42165f7dddff493366fa88355a6b23d8a2 (patch) | |
| tree | 7be1db1ca10d7be835c7f6ce0791b9fd4441cab0 | |
| parent | 0589e3ce7f5ba7c7b756fe748c1d7950e495dd84 (diff) | |
soc/amd/cezanne: populate some FSP-M UPDs
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index f790def747..c7e7e5cba4 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -3,11 +3,22 @@ #include <acpi/acpi.h> #include <arch/cpu.h> #include <console/console.h> +#include <console/uart.h> #include <fsp/api.h> #include <program_loading.h> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); } asmlinkage void car_stage_entry(void) |