From c86acf42165f7dddff493366fa88355a6b23d8a2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 2 Feb 2021 20:21:09 +0100 Subject: soc/amd/cezanne: populate some FSP-M UPDs Signed-off-by: Felix Held Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/romstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index f790def747..c7e7e5cba4 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -3,11 +3,22 @@ #include #include #include +#include #include #include void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); } asmlinkage void car_stage_entry(void) -- cgit v1.2.3