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authorJamie Ryu <jamie.m.ryu@intel.com>2020-06-24 15:55:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-12 19:30:55 +0000
commitef079c86ea3c24dd30d1bbad2e446632ec1c0104 (patch)
tree115c2e656b523d194162f7bc07eb334a5e8fccbc
parent6aedba2f134b8154a342248deae49bc37fc234ce (diff)
mb/intel/tglrvp: Enable CpuReplacementCheck
Enable CpuReplacementCheck for TGLRVP with a CPU socket. Test=build and verified with tglrvp Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 1396d3ac82..612a97d201 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -32,6 +32,9 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
+ # CPU replacement check
+ register "CpuReplacementCheck" = "1"
+
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index c3e41a2644..7a97ad9098 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -32,6 +32,9 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
+ # CPU replacement check
+ register "CpuReplacementCheck" = "1"
+
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"