From ef079c86ea3c24dd30d1bbad2e446632ec1c0104 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Wed, 24 Jun 2020 15:55:10 -0700 Subject: mb/intel/tglrvp: Enable CpuReplacementCheck Enable CpuReplacementCheck for TGLRVP with a CPU socket. Test=build and verified with tglrvp Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1 Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 +++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1396d3ac82..612a97d201 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -32,6 +32,9 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector + # CPU replacement check + register "CpuReplacementCheck" = "1" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c3e41a2644..7a97ad9098 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -32,6 +32,9 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector + # CPU replacement check + register "CpuReplacementCheck" = "1" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" -- cgit v1.2.3