diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-12-07 22:56:47 +0000 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-28 13:37:47 +0000 |
| commit | d0701c96f20d4b3d04c42c13b1e015d6aa27f1d4 (patch) | |
| tree | fe19d614e4c8f4a489da6ff9d7274a0b4e715ff9 | |
| parent | b8cb142ccd1922f8f0a245923eabaed5030048e5 (diff) | |
soc/intel/skylake: Enable CHAP device depending on devicetree
Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.
Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ef16f388d7..2707353225 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -247,6 +247,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(SA_DEVFN_IMGU); params->SaImguEnable = dev && dev->enabled; + dev = pcidev_path_on_root(SA_DEVFN_CHAP); + tconfig->ChapDeviceEnable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); params->Heci3Enabled = dev && dev->enabled; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 319a12b53a..661ed5cd65 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -42,6 +42,10 @@ #define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0) #define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0) +#define SA_DEV_SLOT_CHAP 0x07 +#define SA_DEVFN_CHAP PCI_DEVFN(SA_DEV_SLOT_CHAP, 0) +#define SA_DEV_CHAP PCI_DEV(0, SA_DEV_SLOT_CHAP, 0) + #define SA_DEV_SLOT_GMM 0x08 #define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) #define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) |