diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-03-30 15:56:46 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-01 15:40:36 +0000 |
| commit | 32fc4e350b55b452f07a37475f053546b15c5415 (patch) | |
| tree | 9433585297fd4938f8aef2284935dbb3fb3eaf95 | |
| parent | f63f2f291ba1e85adb89fab3d6a93b38f8595be7 (diff) | |
soc/amd/cezanne: Add device tree support for I2C
This allows the cr50 on guybrush to show up in ACPI.
BUG=b:183737011
TEST=Boot OS and see I2C devices initialized
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/chip.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 261224326e..c2d7af7f61 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -10,6 +10,8 @@ #include <types.h> #include "chip.h" +/* Supplied by i2c.c */ +extern struct device_operations soc_amd_i2c_mmio_ops; /* Supplied by uart.c */ extern struct device_operations cezanne_uart_mmio_ops; @@ -42,6 +44,12 @@ static struct device_operations pci_domain_ops = { static void set_mmio_dev_ops(struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + case APU_I2C1_BASE: + case APU_I2C2_BASE: + case APU_I2C3_BASE: + dev->ops = &soc_amd_i2c_mmio_ops; + break; case APU_UART0_BASE: case APU_UART1_BASE: dev->ops = &cezanne_uart_mmio_ops; |