From 32fc4e350b55b452f07a37475f053546b15c5415 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 30 Mar 2021 15:56:46 -0600 Subject: soc/amd/cezanne: Add device tree support for I2C This allows the cr50 on guybrush to show up in ACPI. BUG=b:183737011 TEST=Boot OS and see I2C devices initialized Signed-off-by: Raul E Rangel Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Mathew King Reviewed-by: Marshall Dawson Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 261224326e..c2d7af7f61 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -10,6 +10,8 @@ #include #include "chip.h" +/* Supplied by i2c.c */ +extern struct device_operations soc_amd_i2c_mmio_ops; /* Supplied by uart.c */ extern struct device_operations cezanne_uart_mmio_ops; @@ -42,6 +44,12 @@ static struct device_operations pci_domain_ops = { static void set_mmio_dev_ops(struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + case APU_I2C1_BASE: + case APU_I2C2_BASE: + case APU_I2C3_BASE: + dev->ops = &soc_amd_i2c_mmio_ops; + break; case APU_UART0_BASE: case APU_UART1_BASE: dev->ops = &cezanne_uart_mmio_ops; -- cgit v1.2.3