mb/prodrive/hermes: Use some board settings from EEPROM

Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:

- DeepSx
- USB power in S5
- Power state after G3

Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 72 insertions, 0 deletions

diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c
index b24dd566f9..f2bbbba46c 100644
--- a/src/mainboard/prodrive/hermes/mainboard.c
+++ b/src/mainboard/prodrive/hermes/mainboard.c
@@ -1,6 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <device/device.h>
+#include <intelblocks/pmclib.h>
+#include <string.h>
+#include <types.h>
+#include "variants/baseboard/include/eeprom.h"
 #include "gpio.h"
 
 /* FIXME: Example code below */
@@ -65,6 +70,66 @@ static void mb_usb2_fp2_pwr_enable(bool enable)
 	gpio_output(GPP_G4, enable);
 }
 
+static void mainboard_init(void *chip_info)
+{
+	const struct eeprom_board_settings *const board_cfg = get_board_settings();
+
+	if (!board_cfg)
+		return;
+
+	config_t *config = config_of_soc();
+	config->deep_s5_enable_ac = board_cfg->deep_sx_enabled;
+	config->deep_s5_enable_dc = board_cfg->deep_sx_enabled;
+}
+
+static void mainboard_final(struct device *dev)
+{
+	const struct eeprom_board_settings *const board_cfg = get_board_settings();
+
+	if (!board_cfg)
+		return;
+
+	/* Encoding: 0 -> S0, 1 -> S5 */
+	const bool on = !board_cfg->power_state_after_g3;
+
+	pmc_soc_set_afterg3_en(on);
+}
+
+#if CONFIG(HAVE_ACPI_TABLES)
+static void mainboard_acpi_fill_ssdt(const struct device *dev)
+{
+	const struct eeprom_board_settings *const board_cfg = get_board_settings();
+
+	if (!board_cfg)
+		return;
+
+	const unsigned int usb_power_gpios[] = { GPP_G0, GPP_G1, GPP_G2, GPP_G3, GPP_G4 };
+
+	/* Function pointer to write STXS or CTXS according to EEPROM board setting */
+	int (*acpigen_write_soc_gpio_op)(unsigned int gpio_num);
+
+	if (board_cfg->usb_powered_in_s5)
+		acpigen_write_soc_gpio_op = acpigen_soc_set_tx_gpio;
+	else
+		acpigen_write_soc_gpio_op = acpigen_soc_clear_tx_gpio;
+
+	acpigen_write_scope("\\_SB");
+	{
+		acpigen_write_method("MPTS", 1);
+		{
+			acpigen_write_if_lequal_op_int(ARG0_OP, 5);
+			{
+				for (size_t i = 0; i < ARRAY_SIZE(usb_power_gpios); i++)
+					acpigen_write_soc_gpio_op(usb_power_gpios[i]);
+			}
+			acpigen_pop_len();
+		}
+		acpigen_pop_len();
+	}
+	acpigen_pop_len();
+}
+#endif
+
 static void mainboard_enable(struct device *dev)
 {
 	/* FIXME: Do runtime configuration once the board is production ready */
@@ -82,8 +147,15 @@ static void mainboard_enable(struct device *dev)
 	mb_usb31_fp_pwr_enable(1);
 	mb_usb2_fp1_pwr_enable(1);
 	mb_usb2_fp2_pwr_enable(1);
+
+	dev->ops->final = mainboard_final;
+
+#if CONFIG(HAVE_ACPI_TABLES)
+	dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt;
+#endif
 }
 
 struct chip_operations mainboard_ops = {
+	.init       = mainboard_init,
 	.enable_dev = mainboard_enable,
 };