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author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2019-09-24 17:56:34 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-26 09:33:00 +0000 |
commit | 7ae4a268eb244ac5ab80ed9db5887fe35b71a49e (patch) | |
tree | 922facd250323ca90f27c5d98ac9dd03efbf8274 /3rdparty | |
parent | 6aea9f9923a0245b96d09fe64204310ba093c749 (diff) |
soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code
All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2
BUG=b:141535133
TEST=Build and boot grunt.
Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to '3rdparty')
0 files changed, 0 insertions, 0 deletions