soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF

PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot.
Setting it to 0xA would cause an extra delay of 20ms compared to 0xF.
The value of time slot is from 0x0 to 0x1F which represents the delay
when reset occurs.

To avoid the delay, change the value from 0xA to 0xF.

This modification is based on chapter 3.7 in the MT8186 functional
specification.

BUG=b:218630683, b:218630684
TEST=the power-off waveform is correct.

Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com>
Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions