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authorTimothy Pearson <tpearson@raptorengineering.com>2017-01-09 14:19:37 -0600
committerTimothy Pearson <tpearson@raptorengineering.com>2017-01-11 00:18:09 +0100
commit8fa624784e3d78e67cf7b4e0e72cb2208c399f0f (patch)
tree78cd839a8f5e461470b2a28c7294cc587630fa44 /.gitmodules
parentbc44178f0240fe2e6165f300674e3e74a021a0b9 (diff)
amd/mct/ddr3: Correctly program maximum read latency
The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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