soc/intel/alderlake: Update CPU microcode patch base address/size

This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.

This is new feature requirement for ADL as per new Mcheck initialization
flow.

BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.

Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions