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author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-07 13:47:47 -0600 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-09 11:49:02 +0000 |
commit | 6db9dccc57637fa8a7ce90a7019e76f8b9e70d1d (patch) | |
tree | 9291874fbe09551f41e885d76f87cf3979148247 /.gitignore | |
parent | 84a156c77e66b995583686e49effb50e39f94f65 (diff) |
soc/intel: Fix microcode loading
Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a
microcode blob with a total_size field set to 0. This appears to be
support for older chipsets, where the size was set to 0 and assumed to
be 2048 bytes. The fix is to change the result of the subtraction to a
signed type, and ensure the following comparison is done without
promoting the signed type to an unsigned one.
Resolves: https://ticket.coreboot.org/issues/313
Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions