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authorJohn Zhao <john.zhao@intel.com>2020-06-11 18:05:23 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-19 21:55:32 +0000
commitb8febf44d1502149cf759286dfe020f45c307be6 (patch)
treed74cdabac5571ebd99544a3917007cc434cb8337 /.clang-format
parent277e11b3906f79123b54c21facd7a41d18bdcb0d (diff)
soc/intel/tigerlake: Update TCSS for SW CM support
This change adds support for SW CM. Add Operating System Capabilities (_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet Protocol tunneling and enable PCIe tunneling as well. Remove Connect Topology(CNTP) command because kernel driver directly works with SW CM Thunderbolt firmware. Update _DSD method for USB4 support across XHCI and PCIe root ports. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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