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/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPDVPD_H__
#define __FSPUPDVPD_H__
#pragma pack(1)
//
// TODO - Port to fit Quark SoC.
//
#define MAX_CHANNELS_NUM 2
#define MAX_DIMMS_NUM 2
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
} DIMM_INFO;
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
typedef struct {
UINT8 Revision;
UINT16 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
UINT8 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
typedef struct {
/** Offset 0x0020
**/
UINT64 Signature;
/** Offset 0x0028
**/
UINT8 Revision;
/** Offset 0x0029
Tseg Size
Size of SMRAM memory reserved.
**/
UINT8 PcdSmmTsegSize;
/** Offset 0x002A
**/
UINT32 PcdPlatformDataBaseAddress;
/** Offset 0x002E
**/
UINT32 PcdPlatformDataMaxLen;
/** Offset 0x0032
**/
UINT8 ReservedMemoryInitUpd[14];
} MEMORY_INIT_UPD;
typedef struct {
/** Offset 0x0040
**/
UINT64 Signature;
/** Offset 0x0048
**/
UINT8 Revision;
/** Offset 0x0049
**/
UINT8 ReservedSiliconInitUpd[183];
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
typedef struct _UPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 Signature;
/** Offset 0x0008
**/
UINT8 Revision;
/** Offset 0x0009
**/
UINT8 ReservedUpd0[7];
/** Offset 0x0010
**/
UINT32 MemoryInitUpdOffset;
/** Offset 0x0014
**/
UINT32 SiliconInitUpdOffset;
/** Offset 0x0018
**/
UINT64 ReservedUpd1;
/** Offset 0x0020
**/
MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0040
**/
SILICON_INIT_UPD SiliconInitUpd;
/** Offset 0x0100
**/
UINT16 PcdRegionTerminator;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
#define FSP_IMAGE_REV 0x00000000
typedef struct _VPD_DATA_REGION {
/** Offset 0x0000
**/
UINT64 PcdVpdRegionSign;
/** Offset 0x0008
PcdImageRevision
**/
UINT32 PcdImageRevision;
/** Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
/** Offset 0x0010
**/
UINT8 UnusedVpdSpace0[16];
/** Offset 0x0020
**/
UINT32 PcdFspReservedMemoryLength;
} VPD_DATA_REGION;
#pragma pack()
#endif
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