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/* $NoKeywords:$ */
/**
* @file
*
* PCIe late post initialization.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbPcieConfig.h"
#include "GnbPcieInitLibV1.h"
#include "GnbPcieInitLibV4.h"
#include "GnbFamServices.h"
#include "PcieLibTN.h"
#include "PciePowerGateTN.h"
#include "PciePortServicesV4.h"
#include "PcieMaxPayloadV4.h"
#include "OptionGnb.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern GNB_BUILD_OPTIONS GnbBuildOptions;
extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
PcieMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------*/
/**
* Callback to init various features on all active ports
*
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in, out] Buffer Not used
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieMidPortInitCallbackTN (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimit (Engine, Pcie);
if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
PcieInitPortForIommuV4 (Engine, Pcie);
}
}
PcieEnableAspm (Engine, Pcie);
if (GnbBuildOptions.CfgMaxPayloadEnable) {
PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie));
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Master procedure to init various features on all active ports
*
*
*
*
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
STATIC
PcieMidPortInitTN (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
PCIE_LINK_SPEED_CAP GlobalSpeedCap;
Status = AGESA_SUCCESS;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortInitCallbackTN,
NULL,
Pcie
);
GlobalSpeedCap = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
Pcie
);
PcieSetVoltageTN (GlobalSpeedCap, Pcie);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Per wrapper Pcie Late Init.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
STATIC
PcieMidInitCallbackTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PciePwrPowerDownUnusedLanes (Wrapper, Pcie);
PciePowerDownPllInL1TN (Wrapper, Pcie);
PciePwrClockGatingV4 (Wrapper, Pcie);
PcieLockRegisters (Wrapper, Pcie);
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Pcie Late Init
*
* Late PCIe initialization
*
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_SUCCESS Topology successfully mapped
* @retval AGESA_ERROR Topology can not be mapped
*/
AGESA_STATUS
STATIC
PcieMidInitTN (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PciePowerGateTN (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIe Mid Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PcieMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlTN (UnhidePorts, Pcie);
Status = PcieMidPortInitTN (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieMidInitTN (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
PciePortsVisibilityControlTN (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
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