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/* $NoKeywords:$ */
/**
* @file
*
* mmOnlineSpare.c
*
* Main Memory Feature implementation file for Node Interleaving
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Main)
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
**/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "OptionMemory.h"
#include "mm.h"
#include "mn.h"
#include "Ids.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE
/*-----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*-----------------------------------------------------------------------------
*/
BOOLEAN
MemMOnlineSpare (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
/* -----------------------------------------------------------------------------*/
/**
*
* Check and enable online spare on all nodes.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return TRUE - No fatal error occurs.
* @return FALSE - Fatal error occurs.
*/
BOOLEAN
MemMOnlineSpare (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
BOOLEAN IsEnabled;
UINT8 FirstEnabledNode;
UINT32 BottomIO;
BOOLEAN RetVal;
MEM_NB_BLOCK *NBPtr;
MEM_PARAMETER_STRUCT *RefPtr;
AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader));
FirstEnabledNode = 0;
IsEnabled = FALSE;
RetVal = TRUE;
NBPtr = MemMainPtr->NBPtr;
RefPtr = NBPtr[BSP_DIE].RefPtr;
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) {
if (!IsEnabled) {
// Record the first node that has spared dimm enabled
FirstEnabledNode = Node;
IsEnabled = TRUE;
}
}
}
if (IsEnabled) {
NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
// If the first node that has spared dimms does not have a system base smaller
// than bottomIO, then we don't need to reset the GStatus, as we don't need to
// remap memory hole.
if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
RefPtr->GStatus[GsbHWHole] = FALSE;
RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
RefPtr->GStatus[GsbSoftHole] = FALSE;
RefPtr->HoleBase = 0;
}
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
if (Node >= FirstEnabledNode) {
// Remap memory on nodes with node number larger than the first node that has spared dimms.
NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
} else {
// No change is needed in the memory map of this node.
// Need to adjust the current system base for other nodes processed later.
NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
// If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
// If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
// and DramMemHoistValid.
// Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
// DramHoleValid.
if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
}
}
}
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
}
NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
}
return RetVal;
}
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